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Running Doom on Our Custom CPU and Going Viral
- dmitrygr 2mo agoFor anyone else curious: custom FPGA-based CPU code but not a custom architecture. This is an RV32I core. The article takes along time to give up this fact.
- zuzululu 2mo agothanks for saving me the time but it is pretty cool to see i'd love to learn more about fpga my goal is to run very old rare consoles
- kryptiskt 2mo agoDeciding on an ISA like RV32I only sets constraints on your architecture, it doesn't give you any of it for free. So I think it's entirely valid to say that it's a custom architecture if they didn't use any pre-existing CPU design. Basically, they had the API interface and implemented everything behind it. I think saying that "it's an RV32I core" vastly underrates the design work that goes into actually implementing an RV32I core from scratch.
- voidUpdate 2mo agoIt's a custom implementation of an existing architecture
- ahartmetz 2mo agoIt's common to call the instruction set just "architecture", or ISA (instruction set architecture) to be more precise. The implementation is commonly called "microarchitecture".
- speed_spread 2mo agoRV32I doesn't define any architecture, it's just an ISA i.e. a software contract that happens to be implementable in hardware. The CPU could run on outer space goop and still be RV32I.
- Brian_K_White 2mo ago"RV32I doesn't define any architecture, it's just an ISA." My friend...
- speed_spread 2mo agoYou are right, 'A' stands for Architecture. _Instruction Set_ Architecture that is. Not CPU architecture. I should have been more clear: > RV32I doesn't define the hardware architecture FTFM - satisfied?
- dmitrygr 2mo agoThe *architecture* is RV32I_Zmmul which is unambiguously neither new nor custom. What you describe (the specific implementation details of a core) is *microarchitecture*. In this case clearly a lot of work was done and it is cool, but the *architecture* is indeed RV32I and not custom I was not undermining anything. I was helping others find the info I sought and took a while to find. This is why i left my comment. Everyone has their own interests. As an example, my thoughts were "whoa... a new architecture... did they write a new compiler or rewrite doom in assembly?" and for that "it is rv32i" would have been a quick answer.
- Dylan16807 2mo agoMaking a particularly good core is hard. Making a core to the minimum risc-v spec is what you do in a single college course. It's what the ISA was designed for.
- ahk-dev 2mo ago[dead]
- sweetjuly 2mo agoAlways a delight seeing Chisel in the wild :)
- Flex247A 2mo agoGreat work! This reminded me of a project I built a while back: a RV32IM emulator in C++ that can boot and run DOOM. Initially I implemented only RV32I, and implementing the M extension provided a massive speedup! If anyone's curious, here's the source code: https://github.com/lalitshankarch/rvcore https://github.com/lalitshankarch/rvcore
- kailpa1 2mo agoNice one! Sounds like a fun project to do. Did you follow any tutorial or guide for this? If so, I would appreciate it if you shared it.
- Flex247A 2mo agoHi, I didn't follow any specific guide on this, but asked ChatGPT about the bare minimum environment needed to run DOOM. From there, I figured out how to execute the instructions using a switch-case and how to make a custom syscall to trigger rendering. I made a post a while back that details the entire process: https://www.reddit.com/r/EmuDev/comments/1t1or4j/doom_runs_on_my_custom_riscv_emulator/ https://www.reddit.com/r/EmuDev/comments/1t1or4j/doom_runs_o...
- kailpa1 2mo agoThanks, am going to check it out.
- sph 2mo agoIf you don't want to delegate the fun of learning to an LLM, here's how I've built a RV64IM simulator in C in a weekend. All you need is an opcode table, the RISC-V specs and to implement each instruction; the good thing of RISC CPUs is that instructions are very simple (i.e. pretty much everything is a variation of `dest = src1 OP src2`) and memory instructions are dedicated. The other cool thing is that there are no "flags". Start with the base instruction set, then you can add M on top later. 64-bit support requires just a handful more instructions to zero/sign extend from 32-bit. Then, wire your simulator to https://github.com/riscv-software-src/riscv-tests https://github.com/riscv-software-src/riscv-tests, and there you have an official test suite. When everything passes, you have a fully-compliant RISC-V CPU. You can at this point tell GCC or Rust or your favourite language to compile to RV32IM and see it run on your simulator. It's a very gratifying process. If you get at this stage, you might want to use the ecall instruction to hard-code I/O operations such as "read from stdin" or "print a character", and there you have a sandboxed CPU that you can target with your favourite programming language. Make it run DOOM (start with https://github.com/ozkl/doomgeneric https://github.com/ozkl/doomgeneric and see which I/O do you need), or turn it into a toy game console; the sky's the limit. --- Here's a copy-paste of the list of resources I have saved in my notes: - https://github.com/libriscv/libriscv https://github.com/libriscv/libriscv A very fast RISC-V VM with sandboxing of memory and syscalls. - https://luplab.gitlab.io/rvcodecjs/ https://luplab.gitlab.io/rvcodecjs/ RISC-V Instruction Encoder/Decoder - https://www.cs.sfu.ca/~ashriram/Courses/CS295/assets/notebooks/RISCV/RISCV_CARD.pdf https://www.cs.sfu.ca/~ashriram/Courses/CS295/assets/noteboo... Reference card - https://cs.brown.edu/courses/csci1952y/2024/assets/docs/riscv-spec-v2.2.pdf https://cs.brown.edu/courses/csci1952y/2024/assets/docs/risc... Spec - https://riscv-software-src.github.io/riscv-unified-db/manual/html/isa/isa_20240411/insts/sd.html https://riscv-software-src.github.io/riscv-unified-db/manual... - ABI: https://lists.riscv.org/g/tech-psabi/attachment/61/0/riscv-abi.pdf https://lists.riscv.org/g/tech-psabi/attachment/61/0/riscv-a... Good luck!
- paulmooreparks 2mo agoVery cool! I just did the same thing, but for a byte-code interpreter for a completely novel ISA I made up a while back (with an assist from Claude). I just haven't made the HN post yet, since I'm doing a bit of cleanup. https://github.com/paulmooreparks/Maize/ https://github.com/paulmooreparks/Maize/ https://paulmooreparks.github.io/Maize/ https://paulmooreparks.github.io/Maize/
- terekhindc 2mo agowhy Zmmul and not full M — is it just fpga area, or did the doom port let you drop div/rem?
- arghunter 2mo agoI'm kinda lazy lol. We are also implementing out-of-order rn, so we want to get a really solid rv32i setup going before adding multiplication, floating point, vector, etc.
- huflungdung 2mo ago[dead]
- Archit3ch 2mo agoReading "Custom CPU" I expected wafer.space, instead of FPGA.
- mithro 2mo agohttps://www.linkedin.com/posts/hirosh-dabui-a5367443_linux-running-on-my-risc-v-asic-first-silicon-ugcPost-7484586796769669120-8JYm/ https://www.linkedin.com/posts/hirosh-dabui-a5367443_linux-r...
- arghunter 2mo agoWe hope to tape it out, along with an NPU and GPU once we raise $10k. Though first we have to find $10k :(
- varispeed 2mo agoI think you need one more zero.
- deton3991 2mo ago[dead]
- _joel 2mo agoCool, I thought this was a CPU custom designed for Doom, but I guess that's just a 486 :) edit: I went to down a quick hole "The historical footnote is that a version of this genuinely happened. SNES Doom shipped with a Super FX 2 in the cartridge, a custom RISC chip with a pixel-plot instruction, because the console's own CPU had no chance. Jaguar and PlayStation ports both moved the rasteriser onto dedicated hardware. Doom's design was shaped by the absence of an FPU, and then hardware kept getting built to catch up with it."
- blastonico 2mo ago> but I guess that's just a 486 *just* a 486. :-(
- toast0 2mo ago> SNES Doom shipped with a Super FX 2 in the cartridge, a custom RISC chip with a pixel-plot instruction, because the console's own CPU had no chance. The Super FX is a custom RISC chip, but it was custom made for Star Fox and used for other projects with refinements.
- arghunter 2mo agoThis is just RV32I-ZMMUL not a custom architecture, bt if you do want to see something from scratch, without any premade ISA or anything, here is an NPU I built: https://www.armaangomes.com/blogs/kernn/ https://www.armaangomes.com/blogs/kernn/
- tantalor 2mo ago> posted a video that got a few million views Anybody got a link to that? Is it this? https://www.instagram.com/armaan.gomes/reel/DatqWKChtnw/?hl=en https://www.instagram.com/armaan.gomes/reel/DatqWKChtnw/?hl=... I was expecting a real video, not some 9 second clip posted to random social media website.
- jervant 2mo ago> instagram > random social media website
- layer8 2mo agoI wonder, if Doom didn’t exist, what would have taken its place for the “can it run X” usage.
- AndrewOMartin 2mo agoDoom 2. And only John "Benevolent hyper-intelligent architect of the post singularity simulation we all live in" Carmack would know why he named it that.
- caruasdo 2mo agoWell, Doom runs everywhere.
- neonmagenta 2mo agoWe need to update Stardew Valleys saloon game to play Doom
- tracker1 2mo agoThat would be kinda sweet.