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Bug 1950764: Work Around Crash on Intel Raptor Lake CPU
- Polizeiposaune 5mo agoDetails of the errata from a comment in the diff: "Write both dist bytes as a single 2-byte store. This avoids the `movb %ch, [mem]` instruction pattern (store from high-byte register alias) that LLVM otherwise emits when dist arrives as a wide register. That pattern triggers the Intel Raptor Lake CPU errata, causing silent 2-byte stores that corrupt the adjacent `len` byte."
- dmitrygr 5mo agomodifying source to avoid an assembly isntr isn't a fix... this need a compiler fix most likely, or a microcode fix, if possible.
- whadawha 5mo agoAnyone have knowledge of whether microcode can be patched on consumer grade Intel CPUs?
- bri3d 5mo agoYes? It is regularly; both the firmware or the OS can deliver updates depending on configuration. The Raptor Lake CPUs in question have gone through an enormous number of microcode revisions already due to quite famous voltage scaling issues; it's unclear if this errata is fallout from or related to a similar root cause or just another issue with the processor.
- altairprime 5mo agohttps://github.com/intel/intel-linux-processor-microcode-data-files https://github.com/intel/intel-linux-processor-microcode-dat... $ echo 1 > /sys/devices/system/cpu/microcode/reload Hot-swappable, even. TIL!
- xxs 5mo agoof course, it's hot-swap material, the microcode is 1st deployed by the bios, then the OS can apply changes as well. Just that it's writable by $ (not #) feels awkward.
- altairprime 4mo ago> Of course it’s hot-swap Microcode updates like this didn’t exist when I first learned sysadmin, so I guess I don’t take such things for granted, sorry!
- deleted 4mo ago[deleted]
- __patchbit__ 5mo agoAt boot time, the following package provides the latest Intel CPU microcode data files on NetBSD. sysutils/intel-microcode-netbsd dmesg shows cpu 0: ucode 0xf0->0xf6 cpu 1: ucode 0xf0->0xf6
- throwaway2037 5mo agoWhy is this downvoted? (At the time of writing, the text is grey, so it has at least a few downvotes.) This is a good question. As others have noted below, yes, and sometimes you can see kernel logging on start-up when the microcode is loaded.
- varispeed 5mo ago[flagged]
- db48x 5mo agoIt’s not elitism, it’s just self defense. Every forum starts out with high–value high–signal low–noise conversations and gradually decays towards low–signal high–noise conversations as new people are brought in. The new people are, by definition, new. They don’t know much if anything yet so they cannot participate meaningfully in advanced topics. Naturally they ask questions in order to fill in the gaps in their knowledge. It is simply unfortunate that the effect is to increase the amount of noise in the forum as each new member asks the same questions over and over again. This leads to the most knowledgeable members of the forum dropping out, as the quality of the discussion drops below the point where it is worth their time. See also “Eternal September”.
- wtallis 5mo agoIt's a dumb question, because it's in reply to a comment that already implies the answer, and it's trivial to find an answer online in less time than it takes to post that question and wait for someone to supply an answer. The subject of CPU microcode update mechanisms is an interesting and relevant topic, but such a shallow, low-effort question is not a good way to promote interesting discussion on that topic.
- whadawha 5mo agoHow did this get past validation at Intel? This is worse than https://en.wikipedia.org/wiki/Pentium_FDIV_bug https://en.wikipedia.org/wiki/Pentium_FDIV_bug
- bri3d 5mo agoThere's another blog post going into more depth about the issue here: https://fgiesen.wordpress.com/2025/05/21/oodle-2-9-14-and-intel-13th-14th-gen-cpus/ https://fgiesen.wordpress.com/2025/05/21/oodle-2-9-14-and-in... where they speculate that it seems to relate to both other clock-related instability on specific Raptor Lake parts and possibly the overarching voltage control problems that the platform had early on; I can't tell entirely from the bug reports whether the behavior reliably reproduces on 100% of Raptor Lakes but the indicators I'm reading point to that it doesn't. It is concerning that Intel didn't get back to Mozilla about it though, since it's certainly a lot more than a one off.
- userbinator 5mo ago"validation? what validation?" https://news.ycombinator.com/item?id=27244941 https://news.ycombinator.com/item?id=27244941 Edit: you should probably read the article I linked first.
- eigenform 5mo agoWell, the FDIV bug is simpler. AFAICT this whole thing is tied up in the relationship between DVFS, silicon aging, and being able to have guarantees about clock reliability. That seems hard to reason about when you give BIOS vendors and users the ability to do over-volting/over-clocking (and of course, it's worse when you are maybe relying on all this in certain situations to try and approach parity with other hardware vendors who are taping out machines on CMOS processes that are more mature than yours).
- moffkalast 5mo agoCommon Raptor Lake L, add it to the pile of oxidation and overvoltage faults. This has to be the most faulty generation in Intel's entire recent manufacturing history.
- happycube 5mo agoIt's the Alder Lake MAX. Originally decent design just pushed too far.
- mike_hock 5mo agoUh ... working around this in each and every piece of software sounds like a non-starter? Intel should be on the hook to fix this.
- Polizeiposaune 5mo agoUse of the "h" register slices (bits 8..15) by compilers is thankfully pretty rare -- otherwise this would have been noticed much sooner! Agner Fog's optimization guide says "Any use of the high 8-bit registers AH, BH, CH, DH should be avoided because it can cause false dependences and less efficient code."
- userbinator 5mo agoUse of the "h" register slices (bits 8..15) by compilers is thankfully pretty rare That's unfortunate, because it's precisely why things like this will keep happening. Agner Fog's optimization guide says "Any use of the high 8-bit registers AH, BH, CH, DH should be avoided because it can cause false dependences and less efficient code." The sad vicious cycle of compilers not exercising the hardware, and then the hardware designers not paying attention. Using the high 8-bit registers and "implicitly merging" them is one of the ways to reduce the number of instructions and thus improve size optimisation.
- fuhsnn 5mo ago> The sad vicious cycle of compilers not exercising the hardware There could theoretically be instruction selection passes that are biased toward rare instructions, specialized for fuzzing hardware, I'm surprised Intel doesn't already do that.
- cesarb 5mo ago> That's unfortunate, because it's precisely why things like this will keep happening. I have the opposite opinion. Its use being rare means CPU designers have less need to optimize for that rare case, and hardware optimizations are precisely where these kinds of issues tend to pop up. And high 8-bit registers are a x86-specific feature, other CPU families don't have it. So that special case being less optimized (or even pessimized) is not much of a loss.
- bri3d 5mo agoLinked in the Bugzilla thread is a really nice in depth investigation of the same issue with high register aliases in a similar algorithm (Huffman coding) but in an entirely different product: https://fgiesen.wordpress.com/2025/05/21/oodle-2-9-14-and-intel-13th-14th-gen-cpus/ https://fgiesen.wordpress.com/2025/05/21/oodle-2-9-14-and-in... . It's concerning that Intel don't seem to have been responsive to anyone with respect to this issue and it doesn't appear to have an official errata yet, although Raptor Lake was the Intel CPU with voltage issues and basically random bit rot so I suppose it's hard to tell if this is a silicon level errata caused by bad design or by some kind of post-manufacturing damage. Raptor Lake in general causes enough non-reproducible noise that I believe Firefox gave up on automated crash reports from it ( https://bugzilla.mozilla.org/show_bug.cgi?id=1975808 https://bugzilla.mozilla.org/show_bug.cgi?id=1975808 ). EDIT: I read that Oodle article (which is SO good!) again and realized that their customer-provided reproduction of the bug was directly linked to boost clock speeds (the customer said that overclocking by 5% made it happen entirely reliably), so this is definitely not a "the architecture has a 100% bug in it" but rather some deeper issue with clock propagation that appears at edge cases.
- deleted 5mo ago[deleted]
- mtlmtlmtlmtl 5mo agoIt's very interesting because my 13900K has worked like a dream from day one and still to this day. Never had any of the voltage issues, never had any abnormal crashes in Firefox or any other software. I was undervolting it for a long while, so I wonder if somehow that saved me from the voltage issues before they were fixed?
- whizzter 5mo agoI remember Puget systems pointed to this same thing when they analyzed the issues back in the day when it was blowing up. https://www.pugetsystems.com/blog/2024/08/02/puget-systems-perspective-on-intel-cpu-instability-issues/ https://www.pugetsystems.com/blog/2024/08/02/puget-systems-p...
- 5mo ago
- userbinator 5mo agoWTF, Intel? This is reminding me of a very similar bug from 9 years ago: https://news.ycombinator.com/item?id=14630183 https://news.ycombinator.com/item?id=14630183 Clearly Intel needs to do far more extensive regression-testing, with things like demoscene productions --- especially the extremely size-optimised ones that can exercise the edge-cases much better than the usual "compiler slop".
- hsbauauvhabzb 5mo agoIntel knowingly sold defective cpus and denied the defect until reports hit critical mass. I don’t think they care.
- userbinator 5mo ago"knowingly" is meaningless, as otherwise they wouldn't even bother releasing errata lists; it's more likely that they underestimated the severity or their planned obsolescence calculations happened to be more statistically favourable than reality. https://news.ycombinator.com/item?id=41041855 https://news.ycombinator.com/item?id=41041855
- hsbauauvhabzb 5mo agoThe link you provided doesn’t match your comment, one of the comments in that thread points out that Intel blamed motherboards during the early stages.
- moffkalast 5mo agoYes let's give a 50 billion dollar corporation flooded with MBAs the benefit of the doubt lmao. If GamersNexus can be believed, it was extremely deliberate to try and sweep it all under the rug. I don't think they've clarified which exact models of which serial number ranges are affected with oxidation to this day. It should've been a recall.
- close04 5mo ago> "knowingly" is meaningless You’re intentionally muddying the waters with meaningless philosophy. Even the law makes the difference between “knowingly” (with knowledge, intention, premeditation) and “mistake”. They didn’t knowingly break the CPU but they knowingly launched it despite their own internal findings, and knowingly blamed others when this came out. But here you are claiming that the company must deserve the benefit of the doubt on their intent. No, “knowingly” is most definitely not “meaningless”. And anyone who’s not naive or bad intentioned should make that difference and take note. Every time a company gets away with it because an army of philosophers washes away any guilt or plays it down with meaningless distinctions it becomes one more reason to do it again. Knowingly.
- robin_reala 5mo agoAlso worth reading this thread on the subject: https://mas.to/@gabrielesvelto/116630047156991279 https://mas.to/@gabrielesvelto/116630047156991279 Regarding the Raptor Lake bug I received a couple of messages from confused users that had read articles on Tomshardware and Neowin. They asked about erratas and microcode updates which puzzled me, because that was part of my early investigation into the bug and we know that the failure is not caused by a known errata and microcode updates cannot fix broken CPUs. So why did they ask? As it turns out it was slop. Both articles are 100% slop full of confusing and inaccurate claims.
- websg-x 5mo agoBecause it's a known problem. It's called Vmin Shift Instability issues. The affected CPUs are broken. One needs to RMA the CPUs. Intel also extended CPU warranty for 2 more years. Because there still are many broken CPUs out in the wild. Firefox works around the crash so the broken CPUs won't flood the channel with crash reports.
- deleted 5mo ago[deleted]
- samlinnfer 5mo agoSorry it's still not clear what he means? When a CPU is "broken", is it already failing or is it "broken" in the sense it will fail? For example: Does he mean all existing 13th/14th gen CPUs (prior to Intel's discovery of the vmin issue) are broken in the sense that they are susceptible to damage and can only be replaced. OR Does he mean that the microcode updates, applied by Intel to existing CPUs that are susceptible to damage, will only slow degradation and the CPUs will eventually fail and can only be replaced. OR Is he saying the 13th/14th gen CPUs which have already sustained damage, cannot be fixed by microcode updates.
- websg-x 5mo agoOnly the desktop 8p+16e cores(13600/700/900,14600/700/900)k are susceptible. The CPUs are safe with the fixed bios/microcode. The notebook version of 8p+16e CPUs are also safe from vmin shift since notebook computer cannot go insane with voltage. If the CPU is damaged already, the new microcode wont fixed the problem. It broken. You have to RMA the CPU. The vmin shift instability is fixed. There are no new report of mass failures of 13th/14th gen CPUs after the new bios/microcode release.
- charcircuit 5mo agoHopefully this bug is getting handled upstream in a microcode update or a compiler fix to avoid emitting such instructions. Just a comment mentioning that you should not emit a particular instruction is not a strong guarantee.
- progval 5mo agoAccording to https://bugzilla.mozilla.org/show_bug.cgi?id=1950764#c23 https://bugzilla.mozilla.org/show_bug.cgi?id=1950764#c23 , it is not getting fixed.
- WaylandYang 5mo ago[flagged]
- codedokode 5mo agoI looked at the Raptor Lake errata [1] and it looks pretty scary. What if someones builds an exploit on these errors? This is why CPU designers should aim for simplicity. This is why RISC-V vector extension, which requires complicated logic, can become a source of implementation errors. [1] https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processor-specification-update/errata-details/ https://edc.intel.com/content/www/us/en/design/products/plat...
- adrian_b 5mo agoAll Intel, AMD or Arm-based CPUs and any other modern CPUs have dozens of errata, even if some CPU vendors keep them secret, instead of publishing them, as they should. Fortunately, most of the erroneous behaviors are triggered only by very unlikely combinations of circumstances, some of which may even be impossible to happen in user programs, but only in operating system kernels. Nevertheless, from time to time there are also serious errata, like the one discussed here, which can be triggered even by ordinary user programs. Sometimes, like here, such errata can be avoided by compilers patched to not generate the buggy instructions for the affected CPU models, assuming that it is known with certainty on which model of computer the compiled program will be executed (or using code dispatch at run time, based on the CPU model). Simplicity in the CPU hardware may reduce the probability of hardware bugs, but it increases the probability of software bugs, because the missing hardware features must be implemented at a much greater cost in software, like in the case with the missing integer overflow detection of RISC-V, which causes most RISC-V programs to omit overflow checks, increasing the chances of undetected bugs.
- codedokode 5mo agoAnd Rust omits overflow check under the same excuse, although overflow was a reason that allowed multiple Linux kernel vulnerabilities.
- GoblinSlayer 5mo agoBuffer overflows are caught by bound checks that don't need integer overflow checks, cf dotnet.
- ahartmetz 5mo agoWait what, they are using Phabricator? I don't think it's particularly bad, I just though it was... particularly dead.