>but if you really think about the models and how they are currently implemented in silicon, they are still inefficient as hell. I'm not sure this follows? Res

>but if you really think about the models and how they are currently implemented in silicon, they are still inefficient as hell. I'm not sure this follows? Research has gone into two bit quantizations that only need a scale factor per block and each parameter merely takes up two bits which means that the operations can be mapped directly onto adders rather than multipliers. >but if you really think about the models and how they are currently implemented in silicon, they are still inefficient as hell. The vast majority of analogue components are both space and energy inefficient. Digital won for a reason. You can simply keep scaling to lower voltages and smaller transistors since you only need to distingish between one and zero.