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Intel's 50-Core Xeon Phi: The New Era of Inexpensive Supercomputing
- cefstat 14y agoI've read about Xeon Phi a few months ago and I really want to get my hands on one. My problems are in the embarrassingly parallelizable class (or almost). Having said that, does anybody know how each Xeon Phi core performs with respect to a modern Intel processor (i7 or Xeon) for standard numerical code (Linpack etc.)?
- rys 14y agoThey're Pentium-class x86 cores and barely any more than front end control processors for the vector hardware. The fact it's x86 is almost incidental, IMHO; the vector ISA is all programmers should really care about on the Phi.
- berkut 14y agoI guess that means they've got primitive (Pentium Pro equivalent) branch predictors and memory pre-fetchers then? Are they even out-of-order? I.e. is it Pentium or Pentium Pro class?
- stonemetal 14y agohttp://www.anandtech.com/show/6451/the-xeon-phi-at-work-at-tacc http://www.anandtech.com/show/6451/the-xeon-phi-at-work-at-t... Each core is a simple in order x86 CPU (derived from the original Pentium) with a 512-bit SIMD unit.
- berkut 14y agoSo the branch predictors will be crap, but thanks to the hyperthreading, it probably won't be noticeable on most workloads...
- apendleton 14y agoMaybe I'm missing something, but do in-order architectures even have much use for branch prediction? They can't speculatively execute based on the outcome of a conditional, right?
- wtallis 14y agoSure they can. Branch prediction allows you to move an instruction along the pipeline before the instruction determining its outcome has been retired. Without branch prediction, every conditional jump will potentially stall the pipeline. With branch prediction, a correctly predicted branch executes quickly, and a mis-predicted branch results in a pipeline flush. Instruction re-ordering is more about taking full advantage of multiple execution units (ALUs, etc.), or not completely stalling the pipeline to wait on a memory fetch.
- rayiner 14y agoThey aren't quite so primitive. The Atom is also a Pentium-class in-order core. It may be Pentium class, but it's also running at ~2 GHz.
- sp332 14y agoI was curious about this, since the point is that you can run "Xeon" code on the Xeon Phi, but the Phi doesn't support SSE, MMX, or AVX so wouldn't you need to recompile to take advantage of the vector hardware?
- mich41 14y agoIIRC they'll be available to OEMs only. Anyway, Intel claimed 2-3x speedups over some unspecified dual socket Xeon system. http://www.tomshardware.com/reviews/xeon-phi-larrabee-stampede-hpc,3342-5.html http://www.tomshardware.com/reviews/xeon-phi-larrabee-stampe...
- joss82 14y agoI'm sure a lot of us here would love to have a cheap supercomputer to perform some heavily parallelizable workloads on our servers. And it this going to dramatically lower the cost of virtual private instances? I really can't wait to see some benchmarks.
- foxhill 14y agocheap it is certainly not. additionally, all the tests i've seen indicate that kepler/tahiti have got little to worry about.
- Scene_Cast2 14y agoGPGPUs are notoriously hard to extract high performance. If you're an enterprise customer with no readily-available GPGPU code, Xeon Phi makes much more sense GPUs for a few reasons. First, the talent pool for HPC x86 programmers is an order of magnitude larger than for expert GPGPU programmers - Xeon Phi is just a virtual x86 server rack with TCP/IP messaging. Second, the amount of time and effort to extract useful performance from GPGPUs is quite a lot; if it's for internal use and you're not selling the code to the masses, you're likely to get the same amount of performance with less time on the Phi, unless you're going for "the best, regardless of money & time". Last, most enterprise customers will want ECC + other compute features. They're sold in the pro-level 3k+ Teslas, which happen to be more expensive than the Phi. Where GPGPU does make sense: consumer-level hardware using already-written software (workstations and hobbyists in particular) and businesses where performance/watt is crucial at any cost.
- mich41 14y agoPhi architecture is closer to a GPU than a rack of x86 servers. With 60 cores reading memory over a common ring bus latency will kill you unless you tile your loops to maximize cache reuse [1], at which point you might as well write a GPU code which preloads blocks of data to local memory and works there. Also, to beat performance of normal x86 CPU you must use vector instructions, what gives you all the little problems GPU warps are known to cause. [1] http://software.intel.com/en-us/articles/cache-blocking-techniques http://software.intel.com/en-us/articles/cache-blocking-tech...
- stephengillie 14y agoWill ARM servers have PCIe slots?
- Symmetry 14y agoA quick Google reveals there are already ARM servers with PCIe slots. http://www.globalscaletechnologies.com/t-openrdudetails.aspx http://www.globalscaletechnologies.com/t-openrdudetails.aspx
- shasta 14y ago8 GB of RAM total?
- CHsurfer 14y agoPerhaps it could be a 'high CPU' micro instance. 16 512MB instance with 3 cores (6 threads) per instance...
- fdej 14y agoSeems pretty good if you compare it to a GPU.
- tsahyt 14y agoThe impressive thing is the memory bandwidth though. That's the one thing I've always loved GPUs for.
- eliben 14y agoI would guess the main goal is to perform parallel scientific computations on a shared chunk of data, not to run multiple web servers & services.
- praveenster 14y agowhy does the url include donkey as the query string?
- erichocean 14y agoThat article is riddled with errors.
- stcredzero 14y agoExamples?
- api 14y agoI wonder if you could use this to run lots and lots of small virtualized nodes? I know that's not the intended use case but I wonder if it's possible and would perform well?
- rbanffy 14y agoMemory bandwidth would limit the performance unless your VMs were running something with a very small memory footprint, about 160 megabytes per instance. Having said that, I've used Unix workstations with less RAM attached than that through much less than 7GBps worth of bus...
- wmf 14y agoPhi's memory bandwidth is very high but its memory capacity is very low (a normal Xeon can drive ~192 GB cheaply).
- sp332 14y agoThe first paragraph mentions that you can boot an OS on each of those cores. Or did you mean something else? Of course memory is tight as rbanffy pointed out, so loading up so much duplicate OS overhead might not be the most productive use. Edit: 1 GHz sounds like plenty until you realize it's in-order execution. This would be noticeably sluggish.
- matthavener 14y agoVMWare has something called "Transparent Page Sharing", which allows VMs to share read only pages. So, it might actually be feasible to start up 50 VMs if they were all running the same software and only had a small amount of private state.
- foxhill 14y agoit may be possible, but it will almost certainly not perform well.
- foxhill 14y agodon't know where the 50 core figure comes from, as a Phi has 60 cores (61 in the "better" model).
- wmf 14y agoUntil a few days ago Intel was saying "over 50" cores; some people forgot to flush their cache.
- JoeAltmaier 14y agoLots of cores means lots of threads - 4 hyperthreads per core. So 200+ threads could be handy in high-bandwidth low-latency situations. E.g. it could make a dandy server for delivering low-latency streams like stock quotes. You would want a new kernel model, where you bound program threads to particular hyperthreads and blocked in user-space on events - so your hyperthread cache was always hot.
- Symmetry 14y agoNot horribly relevant from a software perspective, but as a hardware geek I think the way they're doing threading is really interesting. Big OoO processors like a normal Xeon or a Power7 usually use simultaneous multithreading (SMT) which means that you have instructions from two threads being fed to the execution units every clock cycle, and since they often aren't in contention for the same resources you get higher throughput. Some in-order processors like a Niagra often use block multithreading (BMT) where you run one process until you get a cache miss, then switch to another thread with some delay as the pipeline is flushed. What the Phi is doing is combining those approaches, running two threads simultaneously and switching threads out on cache-misses. This way you only double rather than quadrupaling your control structures, but you don't have your cores entirely unutalized when you're swapping threads. A really nifty compromise, I think.
- Osmium 14y agoI'm really excited about our massively parallel future, not least because I have to run scientific code that would greatly benefit from it. But at the moment it's so hard to program for this sort of thing: can someone explain why, in simple terms, something like OpenCL or CUDA is so damn complicated? Is there any way to avoid having to have a low-level understanding of how a GPU or co-processor works, rather than expecting the vendor to implement an easier to use solution? I'm thinking about, e.g., Matlab's "parfor" (parallel for) command, which is super easy to use. The article states that "All of these [CUDA/OpenCL] problems go away with the Phi. It's a pure x86 programming model that everyone is used to. It's a question of reusing, rather than rewriting, code" but I find it hard to believe I can just drop existing code into it and expect decent performance.
- mturmon 14y agoHave you used OpenMP (http://en.wikipedia.org/wiki/OpenMP http://en.wikipedia.org/wiki/OpenMP)? It has the flavor of parfor -- you identify the embarrassingly parallel loops in your C or Fortran, put in something like #pragma openmp parallel for in front of them, and your code transfers through pretty much intact -- it handles the thread wrappers. You can add other pragmas for the times when you need locking. This is a much less intrusive setup than CUDA; you don't have to worry about loading data, or double/float conflicts. The OpenMP extensions could be a very good fit for scientific programming on this coprocessor.
- Osmium 14y agoThanks; I'll take a look. But OpenMP is CPU-only right? Apple's got their (currently less portable, admittedly) Grand Central Dispatch that does something similar. But as far as I know, if you want portable GPU code your only option is OpenCL, and even then it requires optimisation depending what device you're using it on (or so I've heard).
- foxhill 14y agoOpenMP 4.0 is likely to have support for accelerator devices (i.e, move the necessary data on to the device, run the computation, and move back to the host). in fact, that's one of the methods you can use the Phi right now (intel have extensions to OpenMP) or if you can't be bothered to wait for such a standard, you should have a look at OpenACC[1], which does exactly this, and exists now. you end up adding code like #pragma acc kernels for on top of your for loops, it does the low level work for you. [1] http://www.openacc-standard.org/ http://www.openacc-standard.org/
- deleted 14y ago[deleted]
- rorrr 14y ago> Suggested reatail pricing for the initial model is $2649, with subsequent models expected to cost less than $2000 That's $44.15 per 1 GHz core. AMD FX-6300 Six-Core 3.5GHz is $138 = $23 per core (and much faster cores). Intel Xeon 5148 2.33ghz is $18.
- jlgreco 14y agoHow do differences in supporting-hardware/density change the effective pricing? It seems to me like the Phi cores could end up cheaper once you factor in everything else that you need to get that many cores of something else.
- rorrr 14y agoYou need just three of AMDs CPUs to match the 60 1GHz cores. You can get a quad CPU motherboard relatively cheaply: http://www.ebay.com/itm/Arima-Quad-CPU-16-Core-AMD-Opteron-Motherboard-w-PSU-/110585626008 http://www.ebay.com/itm/Arima-Quad-CPU-16-Core-AMD-Opteron-M... Also don't forget to add the same costs for the Phi solution.
- astrodust 14y agoThe 50-core Xeon sounded great up until the $2600 price tag. You can buy a lot of CPU cores for that much money if you have quad-socket boards like that.
- codewright 14y agoCost of power, power supplies, motherboards, memory, networking equipment, efficiency losses from synchronization, etc...
- drudru11 14y agoOR... just spend ~$1000 and get 3070 cores of what you really need (FLOPS) How? The latest and greatest Nvidia card at your favorite retailer.
- foxhill 14y agoconsumer kepler boards have no double precision hardware, in this case a Phi would destroy it.