15 ms·
Quite a few architectures have a dedicated 0 register.
by shawn_w 6mo ago
Quite a few architectures have a dedicated 0 register.
- signa11 6mo agoindeed. riscv for instance. also, afaik, xor’ing is faster. i would assume that someone like mr. raymond would know…
- pif 6mo agoWhich part of "mathematical operations don’t reset the NaT bit" did you not understand?
- IshKebab 6mo ago> afaik, xor’ing is faster Even tiny tiny CPUs can do sub in one cycle, so I doubt that. On super-scalar CPUs xor and sub are normally issued to the same execution units so it wouldn't make a difference there either.
- tliltocatl 6mo agoOn superscalars running xor trick as is would be significantly slower because it implies a data dependency where there isn't one. But all OOO x86's optimize it away internally.
- IshKebab 6mo agoSub has the same false data dependency.
- lynguist 6mo agoIndeed!! MIPS - $zero RISC-V - x0 SPARC - %g0 ARM64 - XZR
- classichasclass 6mo agoPowerPC: "r0 occasionally" (with certain instructions like addi, though this might be better considered an edge case of encoding)
- matja 6mo agoAlpha: r31, f31
- Findecanor 6mo agoOn 64-bit ARM, the same register number is XZR in some instructions and the stack pointer in others.
- repelsteeltje 6mo agoYep. The XOR trick - relying on special use of opcode rather than special register - is probably related to limited number of (general purpose) registers in typical '70 era CPU design (8080, 6502, Z80, 8086).
- bonzini 6mo agoA move on SPARC is technically an OR of the source with the zero register. "move %l0, %l1" is assembled as "or %g0, %l0, %l1". So if you want to zero a register you OR %g0 with itself.
- classichasclass 6mo agoUnfortunately, 6502 can't XOR the accumulator with itself. I don't recall if the Z80 can, and loading an immediate 0 would be most efficient on those anyway.
- bonzini 6mo agoThe Z80 can do either LD A,0 or SUB A or XOR A, but the LD is slower due to the extra memory cycle to load the second byte of the instruction.
- blywi 6mo agoXOR A absolutely works on Z80 and it's of course faster and shorter than loading a zero value with LD A,0. LD A,0 is encoded to 2 bytes while XOR A is encoded as a single opcode. XOR A has the additional benefit to also clear all the flags to 0. Sub A will clear the accumulator, but it will always set the N flag on Z80.
- classichasclass 6mo agoAh, thanks, I couldn't recall off the top of my head.
- eichin 6mo agoYeah, the article seems to have missed the likely biggest reason that this is the popular x86 idiom - that it was already the popular 8080/Z80 idiom from the CP/M era, and there's a direct line (and a bunch of early 8086 DOS applications were mechanically translated assembly code, so while they are "different" architectures they're still solidly related.)
- monocasa 6mo agoVery few architectures have a NAT bit though.