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Wow, I wish we could post pictures to HN. That chip is HUGE!!!! The WSE-3 is the largest AI chip ever built, measuring 46,255 mm² and containing 4 trillion tra
by ElijahLynn 8mo ago
Wow, I wish we could post pictures to HN. That chip is HUGE!!!!
The WSE-3 is the largest AI chip ever built, measuring 46,255 mm² and containing 4 trillion transistors. It delivers 125 petaflops of AI compute through 900,000 AI-optimized cores — 19× more transistors and 28× more compute than the NVIDIA B200.
From https://www.cerebras.ai/chip https://www.cerebras.ai/chip:
https://cdn.sanity.io/images/e4qjo92p/production/78c94c67be9b480e9e4e39b7c26e8b11da167325-4096x2160.png?auto=format&dpr=2&fit=crop&fp-x=0.5&fp-y=0.5&h=1400&q=75&w=1400 https://cdn.sanity.io/images/e4qjo92p/production/78c94c67be9...
https://cdn.sanity.io/images/e4qjo92p/production/f552d23b565912e206698908c746f5454f9516e8-1070x877.png?auto=format&dpr=2&fit=max&q=75&w=1070 https://cdn.sanity.io/images/e4qjo92p/production/f552d23b565...
- kreelman 8mo agoWooshka. I hope they've got good heat sinks... and I hope they've plugged into renewable energy feeds...
- King-Aaron 8mo agoNope! It's gas turbines
- quaintdev 8mo ago[flagged]
- atonse 8mo agoFor now. And also largely because it's easier to get that up and running than the alternative. Eventually, as we ramp up on domestic solar production, (and even if we get rid of solar tariffs for a short period of time maybe?), the numbers will make them switch to renewable energy.
- thrance 8mo agoFresh water and gas turbines, I'm afraid...
- hugh-avherald 8mo agoMaybe I'm silly, but why is this relevant to GPT-5.3-Codex-Spark?
- deleted 8mo ago[deleted]
- tonyarkles 8mo agoIt’s the chip they’re apparently running the model on. > Codex-Spark runs on Cerebras’ Wafer Scale Engine 3 (opens in a new window)—a purpose-built AI accelerator for high-speed inference giving Codex a latency-first serving tier. We partnered with Cerebras to add this low-latency path to the same production serving stack as the rest of our fleet, so it works seamlessly across Codex and sets us up to support future models. https://www.cerebras.ai/chip https://www.cerebras.ai/chip
- thunderbird120 8mo agoThat's what it's running on. It's optimized for very high throughput using Cerebras' hardware which is uniquely capable of running LLMs at very, very high speeds.
- kumarvvr 8mo agoIs this actually beneficial than, say having a bunch of smaller ones communicating on a bus? Apart from space constraints that is.
- santaboom 8mo agoYes, bandwidth within a chip is much higher than on a bus.
- zamadatix 8mo agoIt's a single wafer, not a single compute core. A familiar equivalent might be putting 192 cores in a single Epyc CPU (or, more to be more technically accurate, the group of cores in a single CCD) rather than trying to interconnect 192 separate single core CPUs externally with each other.
- elorant 8mo agoThere have been discussions about this chip here in the past. Maybe not that particular one but previous versions of it. The whole server if I remember correctly eats some 20KWs of power.
- neya 8mo ago20KW? Wow. That's a lot of power. Is that figure per hour?
- ipython 8mo agoIt’s 20kW for as long as you can afford the power bill
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- ai-christianson 8mo agoIf you run it for an hour, yes.
- neya 8mo agoI asked because that's the average power consumption of an average household in the US per day. So, if that figure is per hour, that's equivalent to one household worth of power consumption per hour...which is a lot.
- codyb 8mo agoWow, I'm staggered, thanks for sharing I was under the impression that often times chip manufacture at the top of the lines failed to be manufactured perfectly to spec and those with say, a core that was a bit under spec or which were missing a core would be down clocked or whatever and sold as the next in line chip. Is that not a thing anymore? Or would a chip like this maybe be so specialized that you'd use say a generation earners transistor width and thus have more certainty of a successful cast? Or does a chip this size just naturally ebb around 900,000 cores and that's not always the exact count? 20kwh! Wow! 900,000 cores. 125 teraflops of compute. Very neat
- fulafel 8mo agoDesigning to tolerate the defects is well trodden territory. You just expect some rate of defects and have a way of disabling failing blocks.
- DeathArrow 8mo agoSo you shoot for 10% more cores and disable failing cores?
- jychang 8mo agoWell, it's more like they have 900,000 cores on a WSE and disable whatever ones that don't work. Seriously, that's literally just what they do.
- fulafel 8mo agoIn their blog post linked in the sibling comment it says the raw number is 970k and they enable 900k (table at the end).
- joha4270 8mo agoMore or less, yes. Of course, defects are not evenly distributed, so you get a lot of chips with different grades of brokenness. Normally the more broken chips gets sold off as lower tier products. A six core CPU is probably an eight core with two broken cores. Though in this case, it seems [1] that Cerebras just has so many small cores they can expect a fairly consistent level of broken cores and route around them [1]: https://www.cerebras.ai/blog/100x-defect-tolerance-how-cerebras-solved-the-yield-problem https://www.cerebras.ai/blog/100x-defect-tolerance-how-cereb...
- dotancohen 8mo ago> 46,255 mm² To be clear: that's the thousandths separator, not the Nordic decimal. It's the size of a cat, not the size of a thumbnail.
- shwetanshu21 8mo agoThanks, I was acutally wondering how would someone even manage to make that big a chip.
- jmalicki 8mo agoIt's a whole wafer. Basically all chips are made on wafers that big, but normally it's a lot of different chips, you cut the wafer into small chips and throw the bad ones away. Cerebras has other ways of marking the defects so they don't affect things.
- ash_091 8mo ago*thousands, not thousandths, right? The correct number is fourty six thousand, two hundred and fifty five square mm.
- Sharparam 8mo agoThis is why space is the only acceptable thousands/grouping separator (a non-breaking space when possible). Avoids any confusion.
- DeathArrow 8mo ago>Wow, I wish we could post pictures to HN. That chip is HUGE!!!! Using a waffer sized chip doesn't sound great from a cost perspective when compared to using many smaller chips for inference. Yield will be much lower and prices higher. Nevertheless, the actual price might not be very high if Cerebras doesn't apply an Nvidia level tax.
- energy123 8mo ago> Yield will be much lower and prices higher. That's an intentional trade-off in the name of latency. We're going to see a further bifurcation in inference use-cases in the next 12 months. I'm expecting this distinction to become prominent: (A) Massively parallel (optimize for token/$) (B) Serial low latency (optimize for token/s). Users will switch between A and B depending on need. Examples of (A): - "Search this 1M line codebase for DRY violations subject to $spec." An example of (B): - "Diagnose this one specific bug." - "Apply this diff". (B) is used in funnels to unblock (A). (A) is optimized for cost and bandwidth, (B) is optimized for latency.
- magicalhippo 8mo agoAs I understand it the chip consists of a huge number of processing units, with a mesh network between them so to speak, and they can tolerate disabling a number of units by routing around them. Speed will suffer, but it's not like a stuck pixel on an 8k display rendering the whole panel useless (to consumers).
- Heathcorp 8mo agoCerebras addresses this in a blog post: https://www.cerebras.ai/blog/100x-defect-tolerance-how-cerebras-solved-the-yield-problem https://www.cerebras.ai/blog/100x-defect-tolerance-how-cereb... Basically they use very small cores compared to competitors, so faults only affect small areas.
- larodi 8mo agoIs all of it one chip? Seems like a waffer with several at least?
- txyx303 8mo agoThose are scribe lines where you usually would cut out chips which is why it resembles multiple chips. However, they work with TSMC to etch across them.
- vagrantstreet 8mo agoWhy is the CEO some shady guy? though https://daloopa.com/blog/analyst-pov/cerebras-ipo-red-flags-galore https://daloopa.com/blog/analyst-pov/cerebras-ipo-red-flags-... "AI" always has some sleazy person behind it for some reason
- amelius 8mo agoYou need the sleazy person because you need a shit-ton of money.
- vagrantstreet 8mo agoI have "shady CEO that doesn't give back to his country or community" fatigue
- lanthissa 8mo agofor cerbras, can we call them chips? you're no longer breaking the wafer we should call them slabs
- amelius 8mo agoThey're still slices of a silicon ingot. Just like potato chips are slices from a potato.
- colordrops 8mo agoMacrochips
- odiroot 8mo agoI can imagine how terribly bad their yield must be. One little mistake and the whole "chip" is a goner.
- tshaddox 8mo agoThey have a blog post called "100x Defect Tolerance: How Cerebras Solved the Yield Problem": https://www.cerebras.ai/blog/100x-defect-tolerance-how-cerebras-solved-the-yield-problem https://www.cerebras.ai/blog/100x-defect-tolerance-how-cereb...
- svnt 8mo agoOne thing is really bothering me: they show these tiny cores, but in the wafer comparison image, they chose to show their full chip as a square bounded by the circle of the wafer. Even the prior GPU arch tiled into the arcs of the circle. What gives?
- xnx 8mo agoBigger != Better
- carter2099 8mo agoI sent this to someone I know knowledgeable about this type of thing, here’s what he had to say, sharing because I thought it was interesting: Pretty cool tech, silicon is very advanced. That said, this is how every wafer comes out of the fab. This process does not dice out individual chips but instead adds interonnects. I doubt they have 100% yield, but probably just don't connect that die. This type of setup is one of the reasons Apple's M series chips are so effective. Their CPU/GPU/RAM are all on one die/directly interconnected instead of going through some motherboard based connector. I think Apple doesn't have them all go through the same process so those are connected via a different process but same layed on silicon direct connection. This solves the problem data centers tend to have of tons of latency for the connections between processors. This is also similar to AMD's infinity fabric of their Zen architecture. It's cool how all of these technologies build from another. It's also all reliant on fab from TSMC who did the heavy lifting is making the process a reality