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You can do it with HW accelerated emulation like Apple did with M1 CPUs. They implemented x86 compatible behavior in HW so the emulation has very good performan
by jezek2 9mo ago
You can do it with HW accelerated emulation like Apple did with M1 CPUs. They implemented x86 compatible behavior in HW so the emulation has very good performance.
Another approach was Transmeta where the target ISA was microcoded, therefore done in "software".
- BlueToth 9mo agoThey said that they implemented x86 ISA memory handling instructions, that substantially sped up the emulation. I don't remember exactly which now, but they explained this all in a WWDC video about the emulation.
- als0 9mo agoNot instructions per se. Rosetta is a software based binary translator, and one of the most intensive parts about translating x86 to ARM is having to make sure all load/store instructions are strictly well ordered. To alleviate this pressure, Apple implemented the Total Store Ordering (TSO) feature in hardware, which makes sure that all ARM load and store instructions (transparently) follow the same memory ordering rules as x86.
- nineteen999 9mo agoIt is funny to hear sometimes though: "Apple created a chip which is not an X86! Its awesome! And the best thing about it is ... it does TSO does like an X86! Isn't that great?"
- dontlaugh 9mo agoOnly some of the time. I think the last time I ran amd64 on my mac was months ago, a game.
- fweimer 9mo agoThere's a Linux patch that exposes it via prctl: https://lore.kernel.org/all/20240410211652.16640-1-zayd_qumsieh@apple.com/ https://lore.kernel.org/all/20240410211652.16640-1-zayd_qums... There's also the CFINV instruction (architectural, part of FEAT_FLAGM), which helps with emulating the x86-64 CMP instruction.
- izacus 9mo agoApple didn't implement x86 ISA in hardware, they have a few instructions that change memory behaviour to make emulation faster.