While the blog post clearly highlights the core benefit of SIMD. >Yet this new family of instructions was able to describe a great deal more work per instructi

While the blog post clearly highlights the core benefit of SIMD. >Yet this new family of instructions was able to describe a great deal more work per instruction – the key benefit of SIMD. It doesn't really explain why it is a benefit. From a ALU perspective, each SIMD lane could in theory execute a different operation. So why would simultaneous instructions as in SIMD ever be a thing? You could just keep cranking up the ILP (instruction level parallelism) by adding more ALUs, naturally extending to MIMD. Each SIMD lane would be equivalent to a full CPU core, so why is everyone stopping short of unlocking even more performance? Because instruction memory (SRAM) is incredibly expensive. By using SIMD you are reducing the number of instructions needed to describe repeating calculations. If you work with 32-bit floats and 512-bit instructions representing 16 lanes, you've made a 16-fold reduction to the required quantity of instruction memory and subsequent fetches from that memory to express the same parallel computation compared to using ILP.