4 ms·

I don't understand the table under Benchmark Results. To compare the quality of two toolchains, the device architecture needs to be the same. "LUT6" vs "LUT4" d

by adwn 1y ago

I don't understand the table under Benchmark Results. To compare the quality of two toolchains, the device architecture needs to be the same. "LUT6" vs "LUT4" doesn't cut it, there's much, much more to the architecture of an FPGA than the width of its look-up tables [1], and even for the "LUT6" category, I see four different devices. [1] Consequently, there's more to FPGA synthesis than LUT mapping, so take the reported results with a huge grain of salt.

tux3 1y ago
They seem to be making their own eFPGA architecture, so there's no vendor tool to compare against for their primary purpose. The closest you'll get is xc7 (Xilinx) vs vendor, one of which is surely Xilinx 7. But the Yosys xc7 support is limited and not the best supported, so it's not a great comparison either.
imtringued 1y ago
Not just that, their device "z1060" doesn't exist outside this blog post. We literally don't know what it is.
- adapteva 1y ago
  Documentation can be found in two places. What else do you need to know? https://github.com/siliconcompiler/logiklib/tree/main/logiklib/zeroasic/z1060 https://github.com/siliconcompiler/logiklib/tree/main/logikl... https://github.com/zeroasiccorp/wildebeest/tree/main/architecture/z1060 https://github.com/zeroasiccorp/wildebeest/tree/main/archite...
  - someguydave 1y ago
    ah so this is misdirection - what they are really showcasing is their own new FPGA asic
    - amluto 1y ago
      They’re showcasing their open-source stack, built on existing tools, for their own FPGA. Imagine if, 25 years ago, a company had designed a new CPU ISA and core and, as part of the development process, ported GCC and done a nice job tuning the existing optimization passes, with the intention of the GCC port being the primary toolchain that commercial users would use. They could write a blog post about it, and it would have been great. Maybe they even would have acknowledged in the blog post that the stack included binutils :)
      - adapteva 1y ago
        Thank you, comment made my day:-)
      - deleted 1y ago
        [deleted]
      - someguydave 1y ago
        in that case, such a company would be wise to include the fact that the "z1060" is a new CPU instead of failing to even mention what it is in their "new GCC port" press release page
adapteva 1y ago
Yeah, this was a big dilemman You can't compare two different compilers for two different hw targets. That would be like benchmarking GCC compiling to ARM with LLVM compiling to x86. Thierry's synthesis scripts are really very clever, and the go way beyond our Platypus FPGA arch. We are realistic that until we have seilicon nobody cares about our arch. Releasing the work as open source, we think someone should adapt the code for all of the other targes I Yosys (xilinx, lattice...etc) so that everyone can benefit. We contribute a lot of code to open source, but as an FPGA vendor we are not going to spend time/money optimizing compilers for our competitors:-)

by adwn 1y ago

tux3 1y ago

They seem to be making their own eFPGA architecture, so there's no vendor tool to compare against for their primary purpose. The closest you'll get is xc7 (Xilinx) vs vendor, one of which is surely Xilinx 7. But the Yosys xc7 support is limited and not the best supported, so it's not a great comparison either.

imtringued 1y ago

Not just that, their device "z1060" doesn't exist outside this blog post. We literally don't know what it is.

adapteva 1y ago
Documentation can be found in two places. What else do you need to know? https://github.com/siliconcompiler/logiklib/tree/main/logiklib/zeroasic/z1060 https://github.com/siliconcompiler/logiklib/tree/main/logikl... https://github.com/zeroasiccorp/wildebeest/tree/main/architecture/z1060 https://github.com/zeroasiccorp/wildebeest/tree/main/archite...
- someguydave 1y ago
  ah so this is misdirection - what they are really showcasing is their own new FPGA asic
  - amluto 1y ago
    They’re showcasing their open-source stack, built on existing tools, for their own FPGA. Imagine if, 25 years ago, a company had designed a new CPU ISA and core and, as part of the development process, ported GCC and done a nice job tuning the existing optimization passes, with the intention of the GCC port being the primary toolchain that commercial users would use. They could write a blog post about it, and it would have been great. Maybe they even would have acknowledged in the blog post that the stack included binutils :)
    - adapteva 1y ago
      Thank you, comment made my day:-)
    - deleted 1y ago
      [deleted]
    - someguydave 1y ago
      in that case, such a company would be wise to include the fact that the "z1060" is a new CPU instead of failing to even mention what it is in their "new GCC port" press release page

adapteva 1y ago

Yeah, this was a big dilemman You can't compare two different compilers for two different hw targets. That would be like benchmarking GCC compiling to ARM with LLVM compiling to x86. Thierry's synthesis scripts are really very clever, and the go way beyond our Platypus FPGA arch. We are realistic that until we have seilicon nobody cares about our arch. Releasing the work as open source, we think someone should adapt the code for all of the other targes I Yosys (xilinx, lattice...etc) so that everyone can benefit. We contribute a lot of code to open source, but as an FPGA vendor we are not going to spend time/money optimizing compilers for our competitors:-)