4 ms·

This is speculation on my part, but: 1. It is non-trivial additional work to add since these are high frequency signals. 2. It is non-trivial additional work

by ryao 1y ago

This is speculation on my part, but: 1. It is non-trivial additional work to add since these are high frequency signals. 2. It is non-trivial additional work to validate. 3. The hardware PCI-E support is likely buggy because it is not well tested and few want to volunteer to spend time working with the SoC supplier on the bugs.

topspin 1y ago
> It is non-trivial additional work to add since these are high frequency signals. And there it is. Yes, PCI-E 3.0 from 2010, 15 years ago, involves 4 GHz wire level signals. A 4x PCI-E connector has four differential pairs of this, not cross-talking, not violating EMC limits, etc. This requires excellent layout and high quality PCBs with enough layers. Never mind 4.0, 5.0... People just do not appreciate what their expectations entail. A recent discussion about "soldered" RAM in the Framework Desktop thread illustrates this, where someone just can't accept that there are reasons for the things board designers do. After you get done routing the display connector, multiple ethernet, USB, DRAM and all the other high frequency stuff on a couple square inches of low cost PCB, there isn't much room for the stretch goal of PCI-E good enough to get through EMI testing. It is possible. Raspberry Pi did it. But it's a question of cost, talent and time-to-market.
- Dylan16807 1y ago
  > And there it is. Yes, PCI-E 3.0 from 2010, 15 years ago, involves 4 GHz wire level signals. A 4x PCI-E connector has four differential pairs of this, not cross-talking, not violating EMC limits, etc. Well this board does have a lane. And that's within spitting distance of USB 3 which has some pretty cheap implementations. Entire USB 3 hubs cost $2.
  - topspin 1y ago
    It does, for M.2, which is really great: much better than an SD card. I was writing generally about the comments I see about these types of low cost boards: we are awash in these products, which is a good thing, but many are not designed with the care, tools, talent and materials necessary to max out high value features like PCI-E, and people frequently complain about the lack of PCI-E, not understanding what is involved. Personally, I'd like to see a "headless" board forgo nearly all of the typical peripherals. Have a 1x PCI-E M.2 for boot, 1x 10/100 Ethernet for a shell, then a number of PCI-E 1x and 4x connectors for whatever one might want. Let an ecosystem of mini PCI-E boards develop around it such that one could plug-in whatever is desired: WiFi/Bluetooth/LoRa, xGB ethernet, USB 3/4/x, HDMI, MIPI, ADC/DAC, etc. It would require someone to develop a SOC intended for this, as opposed to repurposing Broadcom's phone chips and whatnot. But with so many RISC-V SOC manufacturers around now, this is no longer implausible.
    - Dylan16807 1y ago
      My core point is that whatever is involved, it's also involved in $2 aliexpress hubs with probably $.50 chips. If a computer costs more than $20 it can afford to have PCIe lanes. If there's lockin because they're stuck using particular chips, that makes sense. But it's not because there's particular difficulty in dealing with the signal rates of PCIe 3 or at least 2.

by ryao 1y ago

topspin 1y ago

> It is non-trivial additional work to add since these are high frequency signals. And there it is. Yes, PCI-E 3.0 from 2010, 15 years ago, involves 4 GHz wire level signals. A 4x PCI-E connector has four differential pairs of this, not cross-talking, not violating EMC limits, etc. This requires excellent layout and high quality PCBs with enough layers. Never mind 4.0, 5.0... People just do not appreciate what their expectations entail. A recent discussion about "soldered" RAM in the Framework Desktop thread illustrates this, where someone just can't accept that there are reasons for the things board designers do. After you get done routing the display connector, multiple ethernet, USB, DRAM and all the other high frequency stuff on a couple square inches of low cost PCB, there isn't much room for the stretch goal of PCI-E good enough to get through EMI testing. It is possible. Raspberry Pi did it. But it's a question of cost, talent and time-to-market.

Dylan16807 1y ago
> And there it is. Yes, PCI-E 3.0 from 2010, 15 years ago, involves 4 GHz wire level signals. A 4x PCI-E connector has four differential pairs of this, not cross-talking, not violating EMC limits, etc. Well this board does have a lane. And that's within spitting distance of USB 3 which has some pretty cheap implementations. Entire USB 3 hubs cost $2.
- topspin 1y ago
  It does, for M.2, which is really great: much better than an SD card. I was writing generally about the comments I see about these types of low cost boards: we are awash in these products, which is a good thing, but many are not designed with the care, tools, talent and materials necessary to max out high value features like PCI-E, and people frequently complain about the lack of PCI-E, not understanding what is involved. Personally, I'd like to see a "headless" board forgo nearly all of the typical peripherals. Have a 1x PCI-E M.2 for boot, 1x 10/100 Ethernet for a shell, then a number of PCI-E 1x and 4x connectors for whatever one might want. Let an ecosystem of mini PCI-E boards develop around it such that one could plug-in whatever is desired: WiFi/Bluetooth/LoRa, xGB ethernet, USB 3/4/x, HDMI, MIPI, ADC/DAC, etc. It would require someone to develop a SOC intended for this, as opposed to repurposing Broadcom's phone chips and whatnot. But with so many RISC-V SOC manufacturers around now, this is no longer implausible.
  - Dylan16807 1y ago
    My core point is that whatever is involved, it's also involved in $2 aliexpress hubs with probably $.50 chips. If a computer costs more than $20 it can afford to have PCIe lanes. If there's lockin because they're stuck using particular chips, that makes sense. But it's not because there's particular difficulty in dealing with the signal rates of PCIe 3 or at least 2.