Actual performance data on current ASIC processes is hard to find, but even with the quite old and slow Skywater 130 nm process, you can make a 2.5+ GHz oscilla

Actual performance data on current ASIC processes is hard to find, but even with the quite old and slow Skywater 130 nm process, you can make a 2.5+ GHz oscillator.[1] I strongly suspect that with the current 3nm process you could easily do a 4LUT and latch that could clock well above 10 Ghz. If you tiled those in a grid (A BitGrid)... you've got a non-Von Neumann general purpose compute engine that can clock above 10 Ghz, without the need for photonics. It's only when you expect data to be able to cross a chip in a single clock cycle that you need to slow down to the 5 Ghz or so that CPUs run into trouble exceeding. The idea of RAM itself is the bottleneck. If you can load data in one end of a process, and get results out the other end, without ever touching RAM, you can do wonders. [1] https://github.com/adithyasunil26/2.87GHz-MWG-MPW5 https://github.com/adithyasunil26/2.87GHz-MWG-MPW5