4 ms·
Cache-line bursts/beats tend to be standardized to 64B in lots of NoC architectures.
by arrakark 1y ago
Cache-line bursts/beats tend to be standardized to 64B in lots of NoC architectures.
- Dylan16807 1y ago"Network on Chip" okay got it.
- crest 1y agoA 64B cache-line is the same size as an AVX-512 register.
- p_l 1y ago64 byte cache line size matches 64byte single burst transaction on DDR3-5, and ganged dual channel transaction on DDR2. Matching those together means you have a nice 1-to-1 relationship between filling a cache line and single fast memory transaction