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Test Results for AMD Zen 5
- eigenform 1y agoThis reminds me: has anyone ever figured out why Zen 3 was missing memory renaming, but it came back in Zen 4 and Zen 5?
- Tuna-Fish 1y agoAMD had two leapfrogging CPU design teams. Memory renaming was added by the team that did Zen2, presumably the Zen3 team couldn't import it in time for some reason.
- JackYoustra 1y agoAny writeups on why they chose this system, whether its still used today, etc? I'm completely unfamiliar with this style of management.
- throwaway81523 1y agoDunno about writeups but I've worked in that system. Basically the product lifecycle is longer than one product generation. So you get to stay with it through the development, test/release, and maintenance phases, which are arranged to be 2 release cycles. It didn't seem paradoxical or anything. It just made sense.
- Sesse__ 1y agoIt depends on having two CPU teams, though. There are not that many teams in the world that can design a high-performance microprocessor; I would assume that AMD has two and Apple has only one (which is why you got all these fillers with just larger and larger M1s in a trenchcoat, while the team was busy trying to make M3 happen).
- alberth 1y agoWhile an interesting read, the title is a bit misleading since I didn’t see any actual “test results” in the post.
- ooopdddddd 1y agoThe detailed results are in the links at the bottom of the post.
- Someone 1y agoAMD’s documentation for the CPU may or may not state such things as “There are six integer ALUs, four address generation units, three branch units, four vector ALUs, and two vector read/write units”, but even if it does, Agnes Fog runs actual code to check that, and often discovers corner cases that the official documentation doesn’t mention. So, he black box tests the CPU to try and discover its innards.
- titanomachy 1y ago> Agnes Fog Agner
- djoldman 1y agoThey are linked at the bottom of Mr. Fog's post. For example on page 142 of this: https://www.agner.org/optimize/instruction_tables.pdf https://www.agner.org/optimize/instruction_tables.pdf
- ashvardanian 1y ago> All vector units have full 512 bits capabilities except for memory writes. A 512-bit vector write instruction is executed as two 256-bit writes. That sounds like a weird design choice. Curious if this will affect memcpy-heavy workloads. Writes aside, Zen5 is taking much longer to roll out than I thought, and some of AMD's positioning is (almost expectedly) misleading, especially around AI. AMD's website claims Zen5 is the "Leading CPU for AI" (<https://www.amd.com/en/products/processors/server/epyc/ai.html https://www.amd.com/en/products/processors/server/epyc/ai.ht...>), but I strongly doubt that. First, they compare Zen5 (9965), which is still largely unavailable, to Xeon2 (8280), a 2 generations older processor. Xeon4 is abundantly available and comes with AMX, an exclusive feature to Intel. I doubt AVX-512 support with a 512-bit physical path and even twice as many cores will be enough to compete with that (if we consider just the ALU throughput rather than the overall system & memory).
- dragontamer 1y agoWell, when you consider that AVX 512 instructions have 2 or 3 reads per 1 write, there's a degree of sense here. Consider the standard matrix multiplication primitive the FMAC / multiply and accumulate: 3 reads and one write if I'm counting correctly .... (Output = A * B + C, three reads one output).
- rpiguy 1y agoIt may be easier for the memory controller to schedule two narrower writes than waiting for one 512-bit block or perhaps they just didn't substantially update the memory controller and so it still has to operate as it did in Zen 4.
- p_l 1y agoZen 4 memory controllers operate preferably in multiplies of 512bits (single burst on 16n prefetch mode DDR5 channel, 4 channels on consumer Zen4 devices)
- arrakark 1y agoCache-line bursts/beats tend to be standardized to 64B in lots of NoC architectures.
- pbsd 1y agoVector ALU instruction latencies are understandably listed as 2 and higher, but this is not strictly the case. From AMD's Zen 5 optimization manual [1], we have The floating point schedulers have a slow region, in the oldest entries of a scheduler and only when the scheduler is full. If an operation is in the slow region and it is dependent on a 1-cycle latency operation, it will see a 1 cycle latency penalty. There is no penalty for operations in the slow region that depend on longer latency operations or loads. There is no penalty for any operations in the fast region. To write a latency test that does not see this penalty, the test needs to keep the FP schedulers from filling up. The latency test could interleave NOPs to prevent the scheduler from filling up. Basically, short vector code sequences that don't fill up the scheduler will have better latency. [1] https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/software-optimization-guides/58455.zip https://www.amd.com/content/dam/amd/en/documents/processor-t...
- Dylan16807 1y agoSo if you fill up the scheduler with a long line of dependent instructions, you experience a significant slowdown? I wonder why they decided to make it do that instead of limiting size/fill by a bit. What all the tradeoffs were.
- vhcr 1y agohttps://web.archive.org/web/20250726202105/https://www.agner.org/forum/viewtopic.php?t=287&start=10 https://web.archive.org/web/20250726202105/https://www.agner...
- londons_explore 1y ago> Integer vector instructions and floating point vector instructions now have the same latencies. There is very little reason to use integers for anything anymore. Loop counter? Why not make it a double - you never know when you might need an extra 0.5 loops at the end!
- bee_rider 1y agoFinally we can implement BiCGStab intuitively!
- Intralexical 1y agoIntegers aren't for performance. They're for precision (anything financial for example) and occasionally size.
- crest 1y agoAt least historically integer operations also offered lower latency and higher throughput on CPUs. For decades integer addition and bitwise logical operations have been the canonical single-cycle instructions that any microarchitecture could perform at least once per cycle without visible latency while floating point operations and integer multiplication had multi-cycle latency if it was even fully pipelined. Zen 5 breaks several performance "conventions" e.g. AMD went directly from one to three complex scalar integer units (multiplication, PDEP/PEXT, etc.). Intel effectively has two vector pipelines and the shortest instruction latency is a single cycle while Zen 5 has four pipelines with a two cycle minimum latency. That's a *very* different optimisation target (aim for eight instead of two independent instructions in flight) for low level SIMD code going forward despite an identical instruction set.
- sushevff 1y agoTotally. Can’t wait to access the 18463.637th record in my database plus or minus a record or thousand.
- vhcr 1y agoDoubles can represent integers exactly up to 2^52
- varispeed 1y agoIs it better than M4? If a laptop will need to be plugged in to deliver full performance, whilst blasting fans at full throttle, what is the point? (apart from server / workstation use, where you don't like MacOS or need different OS)
- PixyMisa 1y agoPrice.
- heraldgeezer 1y agoWindows laptops? Desktops for gaming? AMD makes the best gaming CPUs with the X3D series.
- KetoManx64 1y agoWhat about actually doing something useful to bring prosuctive?
- bitmasher9 1y agoIf I’m being productive I’d rather have an AMD chip than M4 so I can run Linux comfortably.
- adgjlsfhk1 1y agoZen5 is a beat for compilation workloads
- heraldgeezer 1y agoAMD wins over Intel here too. Most of the workforce use Windows. You can also use Linux if you want on Intel&AMD. M CPUs are great but constrained by Apple.
- crest 1y agoDepends on your usecase. For a thin 14" laptop an M4 is probably the closer sweet spot, but for CPU heavy workloads Apple doesn't offer anything comparable to Threadripper or EPYC (lots of fast cores, enough memory and I/O bandwidth).
- kklisura 1y agoAre there any good resources on how does one obtain all of this information?
- rft 1y agoThe linked PDF in the post contains a section on how the values are measured and a link to the test suite. Search in [1] for "How the values were measured". For another project that measures the same/very similar values you can check out [2]. They have a paper about the tool they are using [3]. There is also AMD's "Software Optimization Guide" that might contain some background information. [4] has many direct attachments, AMD tends to break direct links. Intel should have similar docs, but I am currently more focused on AMD, so I only have those links at hand. [1] https://www.agner.org/optimize/instruction_tables.pdf https://www.agner.org/optimize/instruction_tables.pdf [2] https://www.uops.info/background.html https://www.uops.info/background.html [3] https://arxiv.org/abs/1911.03282 https://arxiv.org/abs/1911.03282 [4] https://bugzilla.kernel.org/show_bug.cgi?id=206537 https://bugzilla.kernel.org/show_bug.cgi?id=206537
- matt_d 1y agoSee https://github.com/MattPD/cpplinks/blob/master/performance.tools.md#microarchitecture https://github.com/MattPD/cpplinks/blob/master/performance.t...
- monster_truck 1y agoThis matches my experience with Zen in basically any generation. Once you've used all of the tricks and exhausted all of the memory and storage bandwidth, you'll still have compute left. It's often faster to use one less core than you hit constraints at so that the processor can juggle them between cores to balance the thermal load as opposed to trying to keep it completely saturated.
- tw1984 1y agothis is very interesting. any chance you have more concrete stats or results? thanks
- Sesse__ 1y agoI had real code that ran with IPC > 6 on Zen 3; I think that's the first time I've seen a modern CPU _really_ be ALU-bound. :-) But it was very unusual, and when I vectorized it, it ran completely different.
- menaerus 1y agoZen3 decode is 4-wide + 8 uOp cache, and dispatch backend is 6 uOps wide. Theoretically, it shouldn't be possible to have IPC larger than 6.
- qwertox 1y agoAt the bottom of the post is a link to a PDF of "The microarchitecture of Intel, AMD, and VIA CPUs - An optimization guide for assembly programmers and compiler makers" [0] You might want to download it and just take a look at it so you know that this content exists. [0] https://www.agner.org/optimize/microarchitecture.pdf https://www.agner.org/optimize/microarchitecture.pdf
- Sesse__ 1y agoGreat, now we just need the uops.info team to do the same. :-)
- ksec 1y agoGiven how Apple's M4 Core can access all of the L2 Cache ( it is shared ) and has a SLC ( System Level Cache ) one could argue it is better to compare it to AMD X3D variant on Cache size. However on Geekbench 6 it is still off by 30-40% per clock. Even if we consider zero performance improvement from M5, it would be a large jump for Zen 6 to catch up. And that is also the case with Qualcomm's Oryon and ARM's own Cortex X93x series. Still really looking forward to Zen 6 on server though. I cant wait to see 256 Zen 6c Core.
- alberth 1y agoIsn’t Zen fab’ed on nodes sizes Apple used 2-3 years ago (since Apple pays for exclusive rights to TSMC for latest & greatest node sizes).
- ksec 1y agoYes. N4 or 5nm Class compared to Apple's N3E or 2nd Gen 3nm. But the gap in IPC remains the same regardless of node. AMD could scale higher or has lower energy usage, it still wouldn't change the performance. Not only is the Zen 5 slower, it also uses more energy to achieve the its results. Thinking about that the gap is staggering.
- kvemkon 1y ago> AMD chips don't have an equivalent to Intel PT. We'd love to add support as soon as they make one. (2022) [1] > since 2013, Intel offers a feature called "intel processor tracing [2] > [not answered] > When will AMD cpus introduce Intel-PT tech or the Intel branch trace store feature? (2024) [3] > [not answered] Is Intel-PT over-engineered and not really needed in practice? [1] https://github.com/janestreet/magic-trace/wiki/How-could-magic-trace-be-made-to-work-on.../ https://github.com/janestreet/magic-trace/wiki/How-could-mag... [2] https://community.amd.com/t5/pc-processors/amd-ipt-intelpt-intel-processor-trace-equivalent/td-p/406867 https://community.amd.com/t5/pc-processors/amd-ipt-intelpt-i... [3] https://community.amd.com/t5/pc-processors/will-amd-cpus-have-technology-introduction-plans-for-intel-cpus/td-p/715541 https://community.amd.com/t5/pc-processors/will-amd-cpus-hav...
- Sesse__ 1y agoI've used Intel PT several times; it's completely unbeatable for some things. In general, Intel is _way_ ahead of AMD in the performance monitoring game. For instance, IBS is a really poor replacement for PEBS (it still hits the wrong instructions, it just re-weights them and this rarely goes well), which makes profiling anything branchy or memory-bound really hard. This is the only real reason why I prefer to buy Intel CPUs still myself (although I understand this is a niche use case!).