5 ms·
If you were a CS student at UIUC in the late 80s your sophomore weed-out class in C and assembly language coding was on this processor. It was a lot more fun to
by joezydeco 1y ago
If you were a CS student at UIUC in the late 80s your sophomore weed-out class in C and assembly language coding was on this processor. It was a lot more fun to write for this core compared to Intel.
And it was the only processor I ever used that had a STRCPY opcode.
- rasz 1y ago>STRCPY opcode. whats wrong with rep movsb?
- saagarjha 1y agoYou'd need to run strlen first.
- joezydeco 1y agoReal men just blast through memory until hitting a zero. If it's there at all.
- cesarb 1y ago> You'd need to run strlen first. I might be a bit rusty in my x86 assembly, but wouldn't "repnz movsb" be the x86 strcpy opcode, for zero-terminated strings?
- rasz 1y agoIf you care at least a little about buffer overflows You will run one anyway.
- saagarjha 1y agoIf you want a strlen+memcpy you are more than welcome to call it yourself
- zackmorris 1y agoI was at UIUC from 1995-99 for ECE and studied Computer Organization and Design 2nd edition by Patterson and Hennessy: https://openlibrary.org/books/OL670149M/Computer_Organization_and_Design https://openlibrary.org/books/OL670149M/Computer_Organizatio... It mainly covered MIPS but most of the concepts were about as minimal as possible. As in, it would be hard to beat the amount of computation per number of pipeline stages. Back then, 4 stages was considered pretty ideal for branch prediction, since misses weren't too expensive. I believe the PowerPC had 4 pipeline stages, but Pentium got up to 20-30 and went to (IMHO) somewhat pathological lengths to make that work, with too much microcode, branch prediction logic and cache. Unfortunately that trend continued and most chips today are so overengineered that they'd be almost unrecognizable to 90s designers. The downside of that being that per-thread performance is only maybe 3 times higher today than 30 years ago, but transistor counts have gone from ~1 million to ~100 billion, so CPUs are about 100,000 times or 5 orders of magnitude less performant than might be expected by Moore's law at a 100x speed increase per decade. Bus speeds went from say 33-66 MHz to 2-4 GHz which is great, but memory was widely considered far underpowered back then. It could have ramped up faster but that wasn't a priority for business software, so gaming and video cards had to lead the way like usual. I always dreamed of making an under $1000 MIPS CPU with perhaps 256-1024 cores running at 1 GHz with local memories and automatic caching using content-addressable hash trees or something similar instead of associativity. That way it could run distributed on the web. A computer like this could scale to millions or billions of cores effortlessly and be programmed with ordinary languages like Erlang/Go or GNU Octave/MATLAB instead of needing proprietary/esoteric languages like OpenCL, CUDA, shaders, etc. More like MIMD and transputers, but those routes were abandoned decades ago. Basically any kid could build an AI by modeling a neuron with the power of ENIAC and running it at scale with a simple genetic algorithm to evolve the neural network topology. I wanted to win the internet lottery and do that, but the Dot Bomb, wealth inequality, politics, etc conspired to put us on this alternate timeline where it feels like the Enterprise C just flew out of a temporal anomaly. And instead of battling Klingons, groupthink has us battling the Borg.