4 ms·

This whole exercise started because I wanted to see if it's possible to add a sniffer to the memory chips of the TDS 684B so that I can use it as the analog fro

This whole exercise started because I wanted to see if it's possible to add a sniffer to the memory chips of the TDS 684B so that I can use it as the analog frontend of a USB scope. It's not possible because of this CCD trick. I've also looked at the existence of CCD memory, but it doesn't seem to be a thing anymore. I didn't find any such modern chips.

amelius 1y ago
Have you checked this category: https://www.digikey.com/en/products/filter/delay-lines/688 https://www.digikey.com/en/products/filter/delay-lines/688
- tverbeure 1y ago
  I didn't know that kind of product existed! I don't think it's useful to slow-sample a fast signal (e.g. they delay digital signals, not analog ones), but some of those chips have a BW of 1.5GHz.
  - amelius 1y ago
    > e.g. they delay digital signals, not analog ones I think they can be used with analog signals too. After all, they are (I suppose) just a chain of transistors holding charge, like in a CCD. It is just the most efficient implementation, since doing it with logic gates will bring more overhead. EDIT: maybe not, it seems at least some of these chips have digital input/output stages. Maybe it could work if you put a very fast 8-bit ADC in front of the delay line, and used 8 delay lines, one for each bit? :) Anyway, I have totally zero experience with these chips. But I can imagine you clock-in the signal using a fast clock (maybe the internal clock), and then you clock-out the signal using a slow clock (slow enough for a subsequent ADC chip). Also, perhaps you can put a bunch of these combinations in parallel to increase bandwidth, or to increase sample depth.
fecal_henge 1y ago
https://www.psi.ch/en/drs https://www.psi.ch/en/drs -not quite the same but similarly novel.
Retr0id 1y ago
My motivations were similar, although for my needs the 15K buffer + GPIB is just about good enough. I am curious about the unpopulated SRAM footprints on the acquisition board though, I wonder if there's any possibility it could be upgraded to 30K.

amelius 1y ago

Have you checked this category: https://www.digikey.com/en/products/filter/delay-lines/688 https://www.digikey.com/en/products/filter/delay-lines/688

tverbeure 1y ago
I didn't know that kind of product existed! I don't think it's useful to slow-sample a fast signal (e.g. they delay digital signals, not analog ones), but some of those chips have a BW of 1.5GHz.
- amelius 1y ago
  > e.g. they delay digital signals, not analog ones I think they can be used with analog signals too. After all, they are (I suppose) just a chain of transistors holding charge, like in a CCD. It is just the most efficient implementation, since doing it with logic gates will bring more overhead. EDIT: maybe not, it seems at least some of these chips have digital input/output stages. Maybe it could work if you put a very fast 8-bit ADC in front of the delay line, and used 8 delay lines, one for each bit? :) Anyway, I have totally zero experience with these chips. But I can imagine you clock-in the signal using a fast clock (maybe the internal clock), and then you clock-out the signal using a slow clock (slow enough for a subsequent ADC chip). Also, perhaps you can put a bunch of these combinations in parallel to increase bandwidth, or to increase sample depth.

fecal_henge 1y ago

https://www.psi.ch/en/drs https://www.psi.ch/en/drs -not quite the same but similarly novel.

Retr0id 1y ago

My motivations were similar, although for my needs the 15K buffer + GPIB is just about good enough. I am curious about the unpopulated SRAM footprints on the acquisition board though, I wonder if there's any possibility it could be upgraded to 30K.