5 ms·
This microcontroller, like all microcontrollers Espressif released in the last few years, uses RISC-V as the ISA.
by snvzz 2y ago
This microcontroller, like all microcontrollers Espressif released in the last few years, uses RISC-V as the ISA.
- platevoltage 2y agoI believe the C series is RISC-V, not the S series.
- colechristensen 2y agoFrom the link >Espressif Systems (SSE: 688018.SH) announced ESP32-C5, the industry’s first RISC-V SoC that supports 2.4 GHz and 5 GHz dual-band Wi-Fi 6, along with Bluetooth 5 (LE) and IEEE 802.15.4 (Zigbee, Thread) connectivity. Today, we are glad to announce that ESP32-C5 is now in mass production.
- hughc 2y agoThis wording is ambiguous- it's the first to support 5GHz, but it's not their first RISC-V core.
- bobmcnamara 2y agoXtensa is a dead end, they said so on ESP32.com when someone pointed out the FPU ABI bottleneck
- platevoltage 2y agoI'm sure you're right. The current s3 chip is based on Xtensa, but it was released in 2020, so I guess the OP's statement is correct.
- bobmcnamara 2y agoEdit: dead end for espressif. Still gonna be in a bunch of DSPs and stuff
- snvzz 2y agoEspressif made a decisive shift to RISC-V[0], effectively abandoning Tensilica. ESP32-S3 was, AIUI, their last non RISC-V chip. It was announced in 2020 and released in 2022. 0. https://www.hackster.io/news/espressif-s-teo-swee-ann-confirms-a-shift-to-risc-v-by-default-unless-we-have-some-special-needs-5e365d49bcc5 https://www.hackster.io/news/espressif-s-teo-swee-ann-confir...
- osrec 2y agoGenuine question: is that a good or bad thing?
- connicpu 2y agoIt's a big plus if you want to write code for it in something like Rust. LLVM support for the architecture they used on their older chips (xtensa) for a very long time required compiling a fork of LLVM and rustc in order to target the chips. It may still, I didn't keep up with the effort to upstream that target. RISC-V is an open architecture that has a lot of people excited so compiler support for it is very good. Though as far as why Espressif is using it, it feels likely they would use it because it means they don't have to pay anyone any royalties for the ISA.
- baby_souffle 2y agoUnless you're a shareholder of arm, hard to see how it's a bad thing.
- bobmcnamara 2y agoThe other core they've used is Xtensa
- bobmcnamara 2y agoIt's a mix. Better compiler support for RISC-V, but everything I've seen from them is a much shorter pipeline than the older Xtensa cores, so flash cache misses hit it harder. Both RISC-V and Xtensa suffer from the lack of an ALU carry bit for the purposes of improving pipelining. But for these small cores it means 64-bit integer math usually takes a few more cycles than a Cortex-M Arm chip
- viraptor 2y agoBut that also depends on what you use it for. If you're after the wifi and IO and other nice things for a mostly idle device - the pipeline is almost irrelevant. Esphome can run on older versions just fine too. On the other hand if you're doing something very optimised and need tight timing around interrupts to drive external hardware - it may matter a lot. So... depends on the project.