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It depends where you get them from. A lot of the dev boards have extra tooling and of course a healthy chunk of "dev tax" unfortunately. Luckily you can find mu
by OneDeuxTriSeiGo 2y ago
It depends where you get them from. A lot of the dev boards have extra tooling and of course a healthy chunk of "dev tax" unfortunately. Luckily you can find much more barebones boards available if you know where to look.
https://www.en.alinx.com/Product/SoC-Development-Boards/Versal-AI-Edge/VD100.html https://www.en.alinx.com/Product/SoC-Development-Boards/Vers...
- _sbrk 2y agoIt's not just that the boards are expensive; you'll also need a Vivado license to create any designs for it. That license is at least several thousand dollars for the Versal devices.
- transpute 2y agoIt's taken many years of reverse engineering, but there's now an efficient OSS toolchain for the smaller Artix7 FPGA family, https://antmicro.com/blog/2020/05/multicore-vex-in-litex/ https://antmicro.com/blog/2020/05/multicore-vex-in-litex/
- tux3 2y agoThis blog doesn't seem to talk about the OSS toolchain, litex/vexriscv are very neat but they don't replace Vivado, right?
- transpute 2y agoLike all open-source, it's an ongoing effort. Bunnie has a comparison, https://www.bunniestudios.com/blog/2017/litex-vs-vivado-first-impressions/ https://www.bunniestudios.com/blog/2017/litex-vs-vivado-firs... > Thanks to the extensive work of the MiSoC and LiteX crowd, there’s already IP cores for DRAM, PCI express, ethernet, video, a softcore CPU (your choice of or1k or lm32) and more.. LiteX produces a design that uses about 20% of an XC7A50 FPGA with a runtime of about 10 minutes, whereas Vivado produces a design that consumes 85% of the same FPGA with a runtime of about 30-45 minutes.. LiteX, in its current state, is probably best suited for people trained to write software who want to design hardware, rather than for people classically trained in circuit design who want a tool upgrade.
- oasisaimlessly 2y agoI think transpute likely meant to link F4PGA[1] or one of the projects it makes use of (Yosys, nextpnr, Project IceStorm, Project X-Ray, etc). [1] https://f4pga.org/ https://f4pga.org/
- transpute 2y agoIs this workgroup currently funded?
- transpute 2y agoThanks for the pointer! DARPA ERI investment was initially directed to US academic teams, while Yosys & related decentralized OSS efforts were barely running on conviction fumes in the OSS wilderness. Glad to see this umbrella ecosystem structure from LF Chips Alliance. Next we need a cultural step change in commercial EDA tools.
- _sbrk 2y agoArtix 7 is simplistic compared to any of the Versal chips. You buy an expensive FPGA and then try using an "open-source" tool chain that exposes 25% of the FPGA's potential. Not a great trade-off, eh?
- imtringued 2y agoThe Versal AI edge SOMs are mildly overpriced. The boards are worth it, but in the embedded space Nvidia is offering the cheapest solutions so an FPGA based application will always need to justify the additional cost for slightly worse performance, by arguing that the application has latency requirements that a GPU cannot help with. GPUs tend to perform worse when you have small batches and frequent kernel launches. This is especially annoying in cases where a simple kernel wide synchronization barrier could solve your problems, but CUDA expects you to not synchronize like that within the kernel, you're supposed to launch a sequence of kernels one after the other. That's not a good solution if a for loop over n iterations turns into n kernel calls.
- agustamir 2y ago> FPGA based application will always need to justify the additional cost for slightly worse performance Do mean FPGA has slightly worse performance? Care to elaborate?
- kcb 2y agoCUDA offers grid wide cooperative groups which can synchronize pretty efficiently. And there's also graphs if you know the kernels you're launching ahead of time.