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They are implying that due to smaller features, the transistors change and if these models still hold for those smaller transistors. Classic hn well akshully.
by sitkack 2y ago
They are implying that due to smaller features, the transistors change and if these models still hold for those smaller transistors.
Classic hn well akshully.
- momoschili 2y agoWell I think both commentators are valid- the effect of shrinking a transistor but keeping the same geometry is probably well captured by this model. Going from a "10 nm" DUV finFET to a "7 nm" EUV finFET, this model probably works quite well whether you're manufacturing using EUV or DUV. I think the crux of the matter is the transition from 7 nm down to our modern nodes, where the major change was not only going from DUV to EUV, but perhaps more importantly the change from finFET to multi-gate or gate-all-around FET (GAAFET), where this model probably needs significant updates to be still valid.
- sitkack 2y agoThe is answer the GP was looking for, thank you.
- wtallis 2y agoThis thesis already covers GAAFETs. What might be problematic is that it's modeling cylindrical GAA structures, when fabs are trying to implement GAA with ribbon/sheet style structures that this model might not be able to handle.
- momoschili 2y agogood point, I didn't read closely enough! The geometry of the GAAFET is definitely changes the physical model a lot (among the most important factors probably?)
- sitkack 2y agoSo did wtallis just invalidate his own admonishment of noosphr's question? This feels like a hn breakthrough.