3 ms·

The surviving "CISC" chips are the ones that where, paradoxically, closer to "RISC" in behaviour due to being less capable early on. Compared to motorla 68k, l

by p_l 2y ago

The surviving "CISC" chips are the ones that where, paradoxically, closer to "RISC" in behaviour due to being less capable early on. Compared to motorla 68k, let alone monsters like VAX or PDP-10, x86 is very RISC-y, and AMD64 and intel/amd performance optimization guides (and general evolution of the platform) only moved it further towards RISC-like operation, with focus on load-store approach and most common memory addressing modes essentially becoming a nice wrapper for load-store around the instruction that can be easily pipelined RISC-style. In fact, one can find nice discussions on why the "beautiful CISCs" like VAX and m68k provided very bad to insane barriers to speedup (m68k decoding honestly looks harder, VAX is a horror movie). A lot of standard performance optimizations when compiling for x86-64 are a lot like "treat it like a RISC with fast optional load/store op in most instructions, but still prefer registers".

imtringued 2y ago
This is the key aspect. RISC Vs CISC is a continuum and it is a continuum even within the ISA. If there are complex and slow instructions that can be replaced by simpler faster instructions, then that is what the compiler is going to emit. The legacy stuff is baggage, but obsolete instructions only cost silicon area, something that is constantly getting more abundant as transistors keep getting smaller. The only real difficulty is variable length instructions. The solution to that is predicting the length of the instructions. This means that there are fast instructions (easy to predict) and slow instructions. The compiler can now avoid emitting them. The price of "CISC" becomes ever more insignificant.
- p_l 2y ago
  Also some classic CISC features (that escaped x86 by virtue of it being a cheap micro ISA originally) can explore into ridiculous stalls in execution. The prime example is probably VAX, whose super orthogonal ISA (another "full CISC" hallmark) could lead to single instruction consuming multiple TLB entries (6 argument, up to 18 indirections assuming the arguments don't cause another page fault due to crossing pages), and another instruction could become longer than memory page. Compare x86 where modern approach is essentially "you get free LEA instruction fused with execution of the main instruction" to the point using LEA instead of certain arithmetic ones is basic optimization

by p_l 2y ago

imtringued 2y ago

This is the key aspect. RISC Vs CISC is a continuum and it is a continuum even within the ISA. If there are complex and slow instructions that can be replaced by simpler faster instructions, then that is what the compiler is going to emit. The legacy stuff is baggage, but obsolete instructions only cost silicon area, something that is constantly getting more abundant as transistors keep getting smaller. The only real difficulty is variable length instructions. The solution to that is predicting the length of the instructions. This means that there are fast instructions (easy to predict) and slow instructions. The compiler can now avoid emitting them. The price of "CISC" becomes ever more insignificant.

p_l 2y ago
Also some classic CISC features (that escaped x86 by virtue of it being a cheap micro ISA originally) can explore into ridiculous stalls in execution. The prime example is probably VAX, whose super orthogonal ISA (another "full CISC" hallmark) could lead to single instruction consuming multiple TLB entries (6 argument, up to 18 indirections assuming the arguments don't cause another page fault due to crossing pages), and another instruction could become longer than memory page. Compare x86 where modern approach is essentially "you get free LEA instruction fused with execution of the main instruction" to the point using LEA instead of certain arithmetic ones is basic optimization