3 ms·
Well, as long as the hardware underneath it also enables the construction of a secure system. I don't think we have any such option right now.
by marcosdumay 2y ago
Well, as long as the hardware underneath it also enables the construction of a secure system.
I don't think we have any such option right now.
- snvzz 2y agoAn example of this is timing side channels. Originating in an effort within seL4[0], there's ongoing work[1] in RISC-V to resolve this. 0. https://sel4.systems//Foundation/Summit/2022/slides/d1_11_fence.t_hardware_support_for_preventing_microarchitectural_timing_channels_Nils_Wistoff.pdf https://sel4.systems//Foundation/Summit/2022/slides/d1_11_fe... 1. https://lf-riscv.atlassian.net/browse/RVS-3569 https://lf-riscv.atlassian.net/browse/RVS-3569