3 ms·
RISC-V has a constant time coding extension (Zkt, https://riscv-software-src.github.io/riscv-unified-db/manual/html/isa/isa_20240411/exts/Zkt.html https://riscv
by rwmj 2y ago
RISC-V has a constant time coding extension (Zkt, https://riscv-software-src.github.io/riscv-unified-db/manual/html/isa/isa_20240411/exts/Zkt.html https://riscv-software-src.github.io/riscv-unified-db/manual...). I believe the idea of this is that your CPU will have a dedicated core that implements Zkt and performs a known set of operations in constant time. I'm not sure that anyone has actually implemented it.
Do other ISAs have anything similar?
- camel-cdr 2y agoNo, this Zkt is part of the application profiles, so expected to be implemented by high perf OoO cores. It just defines that a list of instructions must have "data-independent timing".
- beng-nl 2y agoYes, x86: https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/data-operand-independent-timing-isa-guidance.html https://www.intel.com/content/www/us/en/developer/articles/t...
- touisteur 2y agoOooh has it shipped anywhere already ?
- pclmulqdq 2y agoEverywhere. The constant-time bit defaults to "1" because the current x86 CPUs follow all of the promises of this already. The particular feature here is to allow Intel to make optional optimizations that are not constant-time on the particular subset of instructions. ARM cores also have a similar set of promises.
- IshKebab 2y agoZkt is probably widely implemented even if not declared. Since most RISC-V cores are towards the lower end of the spectrum (in order etc.) you'd have to go to extra effort not to implement it.