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> It may surprise a lot of people to know that the JVM's bytecode is actually very, very much not cleanly mappable back to a normal processor's machine code or
by jraph 2y ago
> It may surprise a lot of people to know that the JVM's bytecode is actually very, very much not cleanly mappable back to a normal processor's machine code or instruction set
I believe this is a very sensible decision: being too close to a real architecture would probably tie the bytecode to similar architectures too much and make it quite useless as opposed to compiling to an actual architecture.
The bytecode being abstract enough is likely a good thing to be able to achieve okay performance everywhere. Like, you wouldn't want the bytecode to specify a fixed number of registers.
What may also surprise many people thinking Java is a bloated language is that the Java bytecode is actually quite simple, straightforward to understand, clean and also very well documented. It's an interesting thing to look into, even for someone not involved day to day in some Java.
- geokon 2y agoI remember learning in school that it's a relatively simple stack machine, but when I look at the instruction set online it's actually ~200 opcodes.. Not what I'd describe as "simple, straightforward"
- renewedrebecca 2y agoThat's fewer opcodes than a 6502 or Z80 microprocessor.
- DonHopkins 2y agoIn the 6502 and Z80, "opcode" refers to the actual machine instruction executed by the CPU, represented by mnemonics (e.g., LDA, STA). Each mnemonic can map to multiple opcode values due to different addressing modes. The 6502 has 56 mnemonics, mapping to about 151 unique opcodes. The Z80 has about 80 distinct mnemonics, mapping to about 158 base opcodes, with extended opcodes (via CB, ED, DD, FD prefixes) pushing the total to around 500. Java bytecode opcodes are symbolic instructions for a virtual stack machine, about 200 in total with a 1:1 mapping from mnemonic to opcode, and just an "wide" extended prefix to extend operand sizes, designed for portability rather than direct hardware execution.