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How much would the Non-Recurrent Cost associated with designing a RISC-V CPU using this 2nm? EDA Tools, Photo-Masks, One Time Chip Design Engineer Cost, Simulat

How much would the Non-Recurrent Cost associated with designing a RISC-V CPU using this 2nm? EDA Tools, Photo-Masks, One Time Chip Design Engineer Cost, Simulation/Virtual Verification and so on. I mean every thing till tape-out.

selectodude 2y ago
3nm was over a half billion. So if costs are going up at the same rate, over a billion dollars. https://semianalysis.com/2022/07/24/the-dark-side-of-the-semiconductor/ https://semianalysis.com/2022/07/24/the-dark-side-of-the-sem...
- monocasa 2y ago
  That article refers to those charts by McKinsey as "incorrect" and instead gives a figure of $50M-$75M for 3nm.
  - deleted 2y ago
    [deleted]
adgjlsfhk1 2y ago
Riscv doesn't need smaller nm. It just needs someone to actually design and release a good core design. 14nm (or 4 or anything in between) is perfectly suffient to make a Riscv chip 10x faster than any Riscv that currently exist.
- zozbot234 2y ago
  14nm or so is kind of a sweet spot for general purpose chip design right now, because later nodes turn out to have higher overall per-transistor cost despite the improvement in density and area. Of course this may well change over time as even finer production nodes get developed and the existing nodes then move closer to the trailing edge.
  - wuschel 2y ago
    Interesting! Could you perhaps point me towards the source where I could read up on the state of the art of chip manufacturing and the implications coming from the respective manufacture processes?
    - zozbot234 2y ago
      Isn't that what sites like the OP are for?
  - mlyle 2y ago
    Of course, on the opposite side: if you have higher Fmax and lower power, you need fewer transistors to get the same characteristics for end users.
  - distances 2y ago
    The article linked in another comment pointed out that cost per transistor keeps falling, and it's just the fast increasing fixed costs that make it seem otherwise. https://semianalysis.com/2022/07/24/the-dark-side-of-the-semiconductor/ https://semianalysis.com/2022/07/24/the-dark-side-of-the-sem...
    - zozbot234 2y ago
      Right, but the "fast increasing fixed costs" are what really matters usually. It's not just perception.
      - Dylan16807 2y ago
        It depends on how big of a run you want to do.
- wuschel 2y ago
  What do you tbink is holding RiscV core design back? Is it the IP situation?
  - fngjdflmdflg 2y ago
    Not a hardware person but I read in an interview with Jim Keller that ISA itself doesn't matter that much for performance. >[Arguing about instruction sets] is a very sad story. It's not even a couple of dozen [op-codes] - 80% of core execution is only six instructions - you know, load, store, add, subtract, compare and branch. With those you have pretty much covered it. If you're writing in Perl or something, maybe call and return are more important than compare and branch. But instruction sets only matter a little bit - you can lose 10%, or 20%, [of performance] because you're missing instructions.[0] I've cited this article a few times already (and seen others cite it) so if this is incorrect I hope someone could correct me here. (I have to assume that you also need some sort of SIMD/Vector these days, which RVA23 has anyway, but aside from that.) I've also read that you can port CPU cores to a different ISAs pretty easily which is what PA Semi did when Apple bought them (M1 devs). So what seems to be missing is for a bunch of senior CPU developers who worked at AMD, Intel, PA Semi/Apple or ARM to just make one for RISC-V. Not sure if that is what you meant by IP here. Tenstorrent could be one such group, and they are building RISC-V CPUs, but their focus seems to be split between that and AI accelerators. China is another good candidate. [0] https://www.anandtech.com/show/16762/an-anandtech-interview-with-jim-keller-laziest-person-at-tesla https://www.anandtech.com/show/16762/an-anandtech-interview-...
    - EncomLab 2y ago
      Keller is just a god tier hardware guy - his ability to leverage deep understanding and then explain incredibly complex issues in a few sentences is incredible. Intel shot themselves in the foot when they let him go.
    - topspin 2y ago
      Most of the same was said by Jim in this live interview: https://www.youtube.com/watch?v=rfFuTgnvwgs https://www.youtube.com/watch?v=rfFuTgnvwgs
- Dylan16807 2y ago
  x86 and Arm don't "need" smaller nm either, but there is always a market in speeding up general purpose CPUs. 10x is cool but when that's still catching up it's not done.
  - mort96 2y ago
    There are already companies making huge, expensive, high-performance chips for x86 and ARM; chips which are operating at the limit of what's physically possible. There aren't chips which do that for RISC-V to my knowledge.
    - Dylan16807 2y ago
      I don't see how that changes things. The end goal is the same. x86 and Arm are much further along, but that doesn't mean they "need" better lithography any more or less than RISC-V "needs" it.

selectodude 2y ago

3nm was over a half billion. So if costs are going up at the same rate, over a billion dollars. https://semianalysis.com/2022/07/24/the-dark-side-of-the-semiconductor/ https://semianalysis.com/2022/07/24/the-dark-side-of-the-sem...

monocasa 2y ago
That article refers to those charts by McKinsey as "incorrect" and instead gives a figure of $50M-$75M for 3nm.
- deleted 2y ago
  [deleted]

adgjlsfhk1 2y ago

Riscv doesn't need smaller nm. It just needs someone to actually design and release a good core design. 14nm (or 4 or anything in between) is perfectly suffient to make a Riscv chip 10x faster than any Riscv that currently exist.

zozbot234 2y ago
14nm or so is kind of a sweet spot for general purpose chip design right now, because later nodes turn out to have higher overall per-transistor cost despite the improvement in density and area. Of course this may well change over time as even finer production nodes get developed and the existing nodes then move closer to the trailing edge.
- wuschel 2y ago
  Interesting! Could you perhaps point me towards the source where I could read up on the state of the art of chip manufacturing and the implications coming from the respective manufacture processes?
  - zozbot234 2y ago
    Isn't that what sites like the OP are for?
- mlyle 2y ago
  Of course, on the opposite side: if you have higher Fmax and lower power, you need fewer transistors to get the same characteristics for end users.
- distances 2y ago
  The article linked in another comment pointed out that cost per transistor keeps falling, and it's just the fast increasing fixed costs that make it seem otherwise. https://semianalysis.com/2022/07/24/the-dark-side-of-the-semiconductor/ https://semianalysis.com/2022/07/24/the-dark-side-of-the-sem...
  - zozbot234 2y ago
    Right, but the "fast increasing fixed costs" are what really matters usually. It's not just perception.
    - Dylan16807 2y ago
      It depends on how big of a run you want to do.
wuschel 2y ago
What do you tbink is holding RiscV core design back? Is it the IP situation?
- fngjdflmdflg 2y ago
  Not a hardware person but I read in an interview with Jim Keller that ISA itself doesn't matter that much for performance. >[Arguing about instruction sets] is a very sad story. It's not even a couple of dozen [op-codes] - 80% of core execution is only six instructions - you know, load, store, add, subtract, compare and branch. With those you have pretty much covered it. If you're writing in Perl or something, maybe call and return are more important than compare and branch. But instruction sets only matter a little bit - you can lose 10%, or 20%, [of performance] because you're missing instructions.[0] I've cited this article a few times already (and seen others cite it) so if this is incorrect I hope someone could correct me here. (I have to assume that you also need some sort of SIMD/Vector these days, which RVA23 has anyway, but aside from that.) I've also read that you can port CPU cores to a different ISAs pretty easily which is what PA Semi did when Apple bought them (M1 devs). So what seems to be missing is for a bunch of senior CPU developers who worked at AMD, Intel, PA Semi/Apple or ARM to just make one for RISC-V. Not sure if that is what you meant by IP here. Tenstorrent could be one such group, and they are building RISC-V CPUs, but their focus seems to be split between that and AI accelerators. China is another good candidate. [0] https://www.anandtech.com/show/16762/an-anandtech-interview-with-jim-keller-laziest-person-at-tesla https://www.anandtech.com/show/16762/an-anandtech-interview-...
  - EncomLab 2y ago
    Keller is just a god tier hardware guy - his ability to leverage deep understanding and then explain incredibly complex issues in a few sentences is incredible. Intel shot themselves in the foot when they let him go.
  - topspin 2y ago
    Most of the same was said by Jim in this live interview: https://www.youtube.com/watch?v=rfFuTgnvwgs https://www.youtube.com/watch?v=rfFuTgnvwgs
Dylan16807 2y ago
x86 and Arm don't "need" smaller nm either, but there is always a market in speeding up general purpose CPUs. 10x is cool but when that's still catching up it's not done.
- mort96 2y ago
  There are already companies making huge, expensive, high-performance chips for x86 and ARM; chips which are operating at the limit of what's physically possible. There aren't chips which do that for RISC-V to my knowledge.
  - Dylan16807 2y ago
    I don't see how that changes things. The end goal is the same. x86 and Arm are much further along, but that doesn't mean they "need" better lithography any more or less than RISC-V "needs" it.