4 ms·

Imo the most "unhinged" cpus for AVX-512 are early batches of Alder Lakes which is the only cpu family that has nearly full coverage of all existing avx-512 sub

Imo the most "unhinged" cpus for AVX-512 are early batches of Alder Lakes which is the only cpu family that has nearly full coverage of all existing avx-512 subsets.

fuhsnn 2y ago
Do they cover anything Sapphire Rapids Xeon's don't? I thought they share the same arch (Golden Cove).
- iamnotagenius 2y ago
  Yes, you are right; I meant "consumer grade cpu".
- suzumer 2y ago
  According to this [1] wikipedia article, the only feature Sapphire Rapids doesn't support is VP2INTERSECT. [1]:https://en.wikipedia.org/wiki/Advanced_Vector_Extensions https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
  - nextaccountic 2y ago
    It seems that there are faster alternatives to it https://arxiv.org/abs/2112.06342 https://arxiv.org/abs/2112.06342 https://www.reddit.com/r/asm/comments/110pld0/fasterthannative_alternatives_for_x86/ https://www.reddit.com/r/asm/comments/110pld0/fasterthannati...
    - hogwarts2025 2y ago
      Or Zen 5. :-p
    - janwas 2y ago
      Note that the article mentions using both outputs of the instruction, whereas the emulation is only able to compute one output efficiently.
Namidairo 2y ago
It's a shame that Intel seemed to really not want people to use it, given they started disabling the ability to use it in future microcode, and fused it off in later parts.
- Aurornis 2y ago
  > It's a shame that Intel seemed to really not want people to use it AVX-512 was never part of the specification for those CPUs. It was never advertised as a feature or selling point. You had to disable the E cores to enable AVX-512, assuming your motherboard even supported it. Alder Lake AVX-512 has reached mythical status, but I think the number of people angry about it is far higher than the number of people who ever could have taken advantage of it and benefitted from it. For general purpose workloads, having the E cores enabled (and therefore AVX-512 disabled) was faster. You had to have an extremely specific workload that didn't scale well with additional cores and also had hot loops that benefitted from AVX-512, which was not very common. So you're right: They never wanted people to use it. It wasn't advertised and wasn't usable without sacrificing all of the E cores and doing a lot of manual configuration work. I suspect they didn't want people using it because they never validated it. AVX-512 mode increased the voltages, which would impact things like failure rate and warranty returns. They probably meant to turn it off but forgot in the first versions.
  - Dylan16807 2y ago
    The reason you had to disable the E cores was... also an artificial barrier imposed by Intel. Enabling AVX-512 only looks like a problem when inside that false dichotomy. You can have both with a bit of scheduler awareness.
  - 867-5309 2y ago
    https://www.reddit.com/r/rpcs3/comments/tqt1ko/clearing_up_some_avx512_misinformation_and_how_to/#t3_tqt1ko-post-rtjson-content https://www.reddit.com/r/rpcs3/comments/tqt1ko/clearing_up_s...
  - adrian_b 2y ago
    They had to disable AVX-512 only because Microsoft was too lazy to rewrite their thread scheduler to handle heterogeneous CPU cores. The Intel-AMD x86-64 architecture is full of horrible things, starting with the System Management Mode added in 1990, which have been added by Intel only because every time Microsoft has refused to update Windows, expecting that the hardware vendors must do the work instead of Microsoft for enabling Windows to continue to work on newer hardware, even when that causes various disadvantages for the customers. Moreover, even if Intel had not said that Alder Lake will support AVX-512, they also had not said that the P-cores of Alder Lake will not support AVX-512. Therefore everybody had expected that Intel will continue to provide backward compatibility, as always before that, so the P-cores of Alder Lake will continue to support any instruction subset that had been supported by Rocket Lake and Tiger Lake and Ice Lake and Cannon Lake. The failure to be compatible with their previous products has been a surprise for everybody.
adgjlsfhk1 2y ago
What about Zen5?
- theandrewbailey 2y ago
  AMD advertised and enabled AVX-512 on all Zen 5 CPUs. You have to resort to workarounds to get AVX-512 working on Alder Lake.
irthomasthomas 2y ago
I think I have two of these sitting in a box, one prototype with avx512 and one retail without. Is it worth me breaking these out for ML experiments and such?

Imo the most "unhinged" cpus for AVX-512 are early batches of Alder Lakes which is the only cpu family that has nearly full coverage of all existing avx-512 subsets.

fuhsnn 2y ago

Do they cover anything Sapphire Rapids Xeon's don't? I thought they share the same arch (Golden Cove).

iamnotagenius 2y ago
Yes, you are right; I meant "consumer grade cpu".
suzumer 2y ago
According to this [1] wikipedia article, the only feature Sapphire Rapids doesn't support is VP2INTERSECT. [1]:https://en.wikipedia.org/wiki/Advanced_Vector_Extensions https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
- nextaccountic 2y ago
  It seems that there are faster alternatives to it https://arxiv.org/abs/2112.06342 https://arxiv.org/abs/2112.06342 https://www.reddit.com/r/asm/comments/110pld0/fasterthannative_alternatives_for_x86/ https://www.reddit.com/r/asm/comments/110pld0/fasterthannati...
  - hogwarts2025 2y ago
    Or Zen 5. :-p
  - janwas 2y ago
    Note that the article mentions using both outputs of the instruction, whereas the emulation is only able to compute one output efficiently.

Namidairo 2y ago

It's a shame that Intel seemed to really not want people to use it, given they started disabling the ability to use it in future microcode, and fused it off in later parts.

Aurornis 2y ago
> It's a shame that Intel seemed to really not want people to use it AVX-512 was never part of the specification for those CPUs. It was never advertised as a feature or selling point. You had to disable the E cores to enable AVX-512, assuming your motherboard even supported it. Alder Lake AVX-512 has reached mythical status, but I think the number of people angry about it is far higher than the number of people who ever could have taken advantage of it and benefitted from it. For general purpose workloads, having the E cores enabled (and therefore AVX-512 disabled) was faster. You had to have an extremely specific workload that didn't scale well with additional cores and also had hot loops that benefitted from AVX-512, which was not very common. So you're right: They never wanted people to use it. It wasn't advertised and wasn't usable without sacrificing all of the E cores and doing a lot of manual configuration work. I suspect they didn't want people using it because they never validated it. AVX-512 mode increased the voltages, which would impact things like failure rate and warranty returns. They probably meant to turn it off but forgot in the first versions.
- Dylan16807 2y ago
  The reason you had to disable the E cores was... also an artificial barrier imposed by Intel. Enabling AVX-512 only looks like a problem when inside that false dichotomy. You can have both with a bit of scheduler awareness.
- 867-5309 2y ago
  https://www.reddit.com/r/rpcs3/comments/tqt1ko/clearing_up_some_avx512_misinformation_and_how_to/#t3_tqt1ko-post-rtjson-content https://www.reddit.com/r/rpcs3/comments/tqt1ko/clearing_up_s...
- adrian_b 2y ago
  They had to disable AVX-512 only because Microsoft was too lazy to rewrite their thread scheduler to handle heterogeneous CPU cores. The Intel-AMD x86-64 architecture is full of horrible things, starting with the System Management Mode added in 1990, which have been added by Intel only because every time Microsoft has refused to update Windows, expecting that the hardware vendors must do the work instead of Microsoft for enabling Windows to continue to work on newer hardware, even when that causes various disadvantages for the customers. Moreover, even if Intel had not said that Alder Lake will support AVX-512, they also had not said that the P-cores of Alder Lake will not support AVX-512. Therefore everybody had expected that Intel will continue to provide backward compatibility, as always before that, so the P-cores of Alder Lake will continue to support any instruction subset that had been supported by Rocket Lake and Tiger Lake and Ice Lake and Cannon Lake. The failure to be compatible with their previous products has been a surprise for everybody.

adgjlsfhk1 2y ago

What about Zen5?

theandrewbailey 2y ago
AMD advertised and enabled AVX-512 on all Zen 5 CPUs. You have to resort to workarounds to get AVX-512 working on Alder Lake.

irthomasthomas 2y ago

I think I have two of these sitting in a box, one prototype with avx512 and one retail without. Is it worth me breaking these out for ML experiments and such?