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A FPGA friendly 32 bit RISC-V CPU implementation
- le-mark 2y agoFits on an ICE-40 fpga, that’s not nothing!
- IshKebab 2y agoHow does it compare to the many other RISC-V CPUs?
- tliltocatl 2y agoThe code is much more readable and modular than you typical verilog dump, so it's probably the best CPU for microarchitecture experimentation. Source: did my master thesis prototyping a specialized cache. Started on Rocket Core, which turned out to be a total mess with all of the pipeline in a single module, basically impossible to introduce a new datapath without rewriting everything. Vex was a breath of fresh air. Spinal is also awesome, lots of QoL features for separating concerns between modules in a way that's impossible on Verilog and fixes lots of rough edges of Chisel. Performance on FPGA was better than most open-source RISC-V cores out there as of 2020. Rocket might have been better on silicon, but that's it. I haven't looked much into it since then through.
- dboreham 2y agoSaw .scala files and thought "some verilog thing that uses that extension". Nope. Lots of Scala. That's not what I expected!
- nomad86 2y agoIt reminded me of how, a long time ago, FPGAs were used in Bitcoin mining.
- TheAmazingRace 2y agoI thought it was ASICs?
- zoenolan 2y agoCPU to GPU to FPGA to ASIC All the acronyms
- davidjade 2y agoThere is a successor project as well: https://github.com/SpinalHDL/VexiiRiscv https://github.com/SpinalHDL/VexiiRiscv
- 15155 2y agoAnd a spiritual sibling: https://github.com/SpinalHDL/NaxRiscv https://github.com/SpinalHDL/NaxRiscv
- bri3d 2y agoThe most interesting thing about this isn’t that it’s a RISC-V implementation but that it’s written in a Scala HDL language, SpinalHDL. There are quite a few of these now - Chisel (which Spinal forked from long ago), Amaranth (Python), and Clash (Haskell) all come to mind.
- dailykoder 2y agoDo those languages get used in the industry, except of academia? There are so many HDLs and I am wondering if there is any other benefit of learning any of these, except of possible fun.
- almostgotcaught 2y agono matter what anyone says to you on here (or elsewhere on the blagosphere): no. the answer is absolutely flat out no.
- oldgradstudent 2y agoNo is a good first approximation. There is a little bit of industry usage, with the biggest user being SiFive - the founders come from the UC Berkeley group that developed Chisel. Also, VexRiscv has some industry presence.
- almostgotcaught 2y ago> There is a little bit of industry usage, with the biggest user being SiFive do ask sifive how much they regret that decision though <shrug>
- foota 2y agoThis is off topic, but I recognize your username from a thread a couple weeks ago but your account is relatively new. Out of curiosity did you just find hacker news and decide to make an account, or is this a new alias and you have an older account? I guess I'd be surprised if there's still new people joining lol.
- vollbrecht 2y agoI find it fascinating, calling a CPU implementation FPGA friendly. I don't know why everybody always wants to run soft CPU's on an FPGA. I mean I understand that its nice for the development stage of a CPU, but for all practical purposes, a FPGA is a thing where you can do hyper specialized things in massively parallel fashion, and essentially don't do something to run general purpose code. I am not saying that people should stop doing this things, everybody is free to do what they want, still i don't understand why most of FPGA talks are about soft CPU's when the really interesting stuff is something completely different.
- 15155 2y agoThis has nothing to do with performance or hardware CPU development. FPGA-specific soft cores like VexRiscv and NaxRiscv are immensely useful for anything involving state machine logic or glue code that you do not want to implement in-fabric. Peripherals like on-chip MMCMs/PLLs, on-board I2C and SPI peripherals, etc. with complicated initialization routines or communication flows or sequencing are very easily handled in a soft CPU. Soft CPUs can also be used like high-powered programmable in-circuit logic analyzers: without rebuilding a potentially massive FPGA bitstream, you can probe/observe/inspect, inject/alter any signals or buses you pipe to the CPU. VexRiscv is far more pleasant to use than any vendor ILA IP. Soft CPUs also normally utilize FPGA LUTRAM/BRAM resources, enabling whatever program to run with hard real-time latency consistency.
- almostgotcaught 2y agothis guy gets it - softcores are for giving people access to your IP without forcing them write their own RTL. it's literally the exact same thing as an embedded scripting language (i.e., vm interpreter.......) in a C/C++ program.
- sdvsfqe 2y agoAlso, soft cpus without strict performance and power requirements are really easy to implement with modern toolchains. In one quarter you can take an undergraduate who doesn't even know digital design and have them make a cpu core as a final project, and they can make a decent one. HW is actually really hard. If you can use a soft core to simplify the overall design and suck up a bunch of peripheral logic it's probably a good idea. Then the engineers can spend their time focusing on getting the hard parts of the design correct.
- disdi 2y agoLatest presentation on this topic by main developer: https://youtu.be/dR_jqS13D2c?si=bbZf7Oo5a3JsINYs https://youtu.be/dR_jqS13D2c?si=bbZf7Oo5a3JsINYs
- tverbeure 2y ago6 years ago, I wrote an in-depth blog post about the design principles of the Vexriscv. It’s unlike any other CPU I’ve seen. https://tomverbeure.github.io/rtl/2018/12/06/The-VexRiscV-CPU-A-New-Way-To-Design.html https://tomverbeure.github.io/rtl/2018/12/06/The-VexRiscV-CP...
- nynx 2y agoDo you still use spinal? Have there been other advances in HDL that you've seen over the last 6 years?
- tverbeure 2y agoYes, I still use it for all my hobby projects but I don't use any of the advanced techniques that are used in the Vexriscv. My Scale knowledge is way too limited for that. I use SpinalHDL as a more efficient way to write pure RTL.
- awjlogan 2y agoThis was a really interesting read, thanks.
- phendrenad2 2y agoWhat does "FPGA friendly" mean? I tried to figure it out from the README, which says "Implement multiplication using multiple sub multiplication operations in parallel ("FPGA friendly")". Put another way: what is the FPGA-UNfriendly way to do multiplication?
- phire 2y agoMost FPGAs have converged on 18 bit wide multiplier blocks. If you ask for a 64 bit multiplier, the router will automatically chain together four multiplier blocks and add them together in a single cycle, which is really going to hurt your maximum clock speed (fmax). VexRiscv is aware of this unofficial standard, and asks for four 16x64 multiplies and adds the result together on the next cycle. This produces a much better fmax on FPGAs, but if you were targeting an ASIC, you would be better off asking for a 64-bit multiplier, or not trying for a single-cycle multiply. Most modern CPUs tend to target a 3 cycle pipelined multiplication, which means 22-bit wide multipliers. Doing this on an FPGA each 22-bit multiplication would require two 18-bit multiplier blocks, for a total of six multipliers, wasting more resources. ----- In general, "FPGA friendly" means optimizing your design to take advantage of the things which are cheap on FPGAs, like the 18-bit wide multipliers and the block ram. Such designs tend to run faster on FPGAs and use less resources, but it's wasteful to synthesize them to ASICs.
- cjbillington 2y agoIt took me to the end of your comment to realise the crucial bit I was missing: that they're talking about implementing the CPU on an FPGA. As opposed to, say, interfacing with an FPGA which could be totally different way to be "FPGA-friendly".