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If anyone wants to play arround with simulating it, here is a Dockerfile I use: # Dockerfile FROM ubuntu:24.04 RUN apt-get update && apt-get insta
by camel-cdr 2y ago
If anyone wants to play arround with simulating it, here is a Dockerfile I use:
# Dockerfile
FROM ubuntu:24.04
RUN apt-get update && apt-get install -y build-essential clang libclang-dev llvm-dev cmake libspdlog-dev vim git curl wget time default-jre default-jdk
RUN git clone --recursive https://github.com/OpenXiangShan/xs-env
WORKDIR /xs-env
RUN sed 's/apt\S* install/\0 -y/g;s/source /. /g;s/sudo //g' -i ./*.sh
RUN . ./env.sh && sed 's/\/master/\/master/g;s/$/; cd \/xs-env/g' -i ./update-submodule.sh && ./update-submodule.sh
RUN . ./env.sh && ./setup-tools.sh
RUN . ./env.sh && . ./install-verilator.sh
RUN . ./env.sh && sed 's/^git submodule.*$//g;s/env.*$//g' -i ./setup.sh && . ./setup.sh
RUN . ./env.sh && make -C XiangShan init
RUN . ./env.sh && cd DRAMsim3 && mkdir build && cd build && cmake -D COSIM=1 .. && make -j 8
RUN . ./env.sh && make -C XiangShan emu CONFIG=DefaultConfig WITH_DRAMSIM3=1 MFC=1 -j 8
RUN . ./env.sh \
&& sed 's/unknown-//g;s/rv64gc/rv64gcv/g' -i $AM_HOME/am/arch/*.mk $AM_HOME/am/arch/isa/*.mk \
&& sed 's/define MSTATUS_FS.*$/define MSTATUS_FS 0x6600/g' -i $AM_HOME/am/src/*/isa/riscv/boot/*.S
WORKDIR nexus-am/apps/hello
RUN make ARCH=riscv64-xs
# $NOOP_HOME/build/emu --no-diff -i ./build/hello-riscv64-xs.bin 2>/dev/null
Make sure you have 64GB of RAM. I only had 16GB, but allocating additional 48GB of swap worked.
There are probably some redundant steps, but this worked for me last time I tried.
- ge96 2y agowhy so much ram?
- deleted 2y ago[deleted]
- chrsw 2y ago64GB of RAM isn't that much for full chip simulation of a "high performance" CPU.
- ge96 2y agoyeah I'm super ignorant here, wondering, say you simulated this, could you run a VM OS against it? What kind of scale it it, personal computer or server (i7/xeon)? Or you just use it to compile programs against it? edit: I did skim the readme, I saw verilog makes me think FPGA
- chrsw 2y agoYou could simulate this on an FPGA platform, those aren't going to be cheap to hold a large design. Usually by running simulations on a PC you're just running very specific test cases. I've run CPU simulations on machines with 64GB of RAM before and it took several hours just to get to single-user shell in Linux. Different CPU design and computer, but the point is it's not something you'd typically use interactively.
- ge96 2y agoInteresting do it actually runs that's cool vs. a hyper visor which idk the difference but yeah
- brucehoult 2y agoIf you're simulating a complex CPU's HDL in Verilator then think in terms of single digit thousands of instructions per second. Vs single digit billions of instructions per second when it's made into an SoC. i.e. on the order of a million times slower than the final product. On an FPGA you might get 20 to 50 million instructions per second, only 100 times slower than the final SoC product. But for a large modern OoO design you'll need an FPGA costing $15000 (for a VCU118) or even more.
- IshKebab 2y agoThat's a pretty huge amount of RAM even for a high performance core. The medium performance cores I've simulated use more like 300MB. I suspect it is the Scala compilation that requires all the RAM rather Verilator or the simulator.
- chrsw 2y agoMaybe, I've never used Scala before. But in my experience simulations are way more resource intensive than compilation.
- EastonMan 2y agoNo, the RAM is mainly used by verilator partitioning simulation logic to multiple threads. The Scala part (Chisel -> FIRRTL) runs pretty happy with a few gigs of RAM.
- sdbbp 2y agoThat's the HDL, and not the inherent design complexity.
- camel-cdr 2y agoThe 64GB is for compilation. simulating does take almost no RAM. I can have 12 seperate instances simulating at once and take less than 2GB: https://i.postimg.cc/XqnhcXX1/1-1.png https://i.postimg.cc/XqnhcXX1/1-1.png
- tormeh 2y agoCompiling the chip, right, not the code?
- camel-cdr 2y agoyes
- chrsw 2y agoWow, it's surprising to me there's a huge difference and in that direction. I always used to increasing resource requirements for synthesis->P&R->logic simulation->full chip simulation. I guess times have changed since I worked on chip design.