5 ms·

Cerebras is well-known in the AI chip market. They make chips that are an entire wafer. https://spectrum.ieee.org/cerebras-chip-cs3 https://spectrum.ieee.org/

Cerebras is well-known in the AI chip market. They make chips that are an entire wafer. https://spectrum.ieee.org/cerebras-chip-cs3 https://spectrum.ieee.org/cerebras-chip-cs3

alephnerd 2y ago
Yep! Them, SambaNova, and Groq are super exciting mid-late stage startups imo.
- Der_Einzige 2y ago
  Shhhhh, stop telling the normies about the future! And especially don't tell them to start looking into who "sovereign clouds" actually are!
ericd 2y ago
Interesting that they’ve scaled on-chip memory sublinearly with the growth of transistors between their generations, I would’ve thought they would try to bump that number up. Maybe it’s not a major bottleneck for their training runs?
- jrk 2y ago
  SRAM is scaling significantly more slowly than logic in recent process nodes.
  - ericd 2y ago
    Ahh that explains it, thanks. Seems like a potentially large problem given their strategy.
    - phonon 2y ago
      They could use something like GCRAM[1] to double capacity if they had to...but it's not clear how much worse performance would be. [1]https://raaam-tech.com/products/ https://raaam-tech.com/products/
      - nsteel 2y ago
        The performance doesn't look great (yet). See Fig. 7 https://www.eng.biu.ac.il/fishale/files/2020/12/A-1-Mbit-Fully-Logic-Compatible-3T-Gain-Cell-Embedded-DRAM-in-16-nm-FinFET.pdf https://www.eng.biu.ac.il/fishale/files/2020/12/A-1-Mbit-Ful...
        phonon 2y ago
        Cerebras runs at 1.1 GHz[1], and this was a much earlier design on 16nm so it might be a good fit by now. Their TSMC 5 nm version is scheduled for early 2025.[2] [1]https://cerebras.ai/blog/cerebras-architecture-deep-dive-first-look-inside-the-hw/sw-co-design-for-deep-learning https://cerebras.ai/blog/cerebras-architecture-deep-dive-fir... [2]https://www.eenewseurope.com/en/raaam-signs-lead-licensee-for-sram-replacement-technology/ https://www.eenewseurope.com/en/raaam-signs-lead-licensee-fo...
        nsteel 2y ago
        They'd have to quadruple their performance to be relevant in the market generally, here's to hoping.
        phonon 2y ago
        Yeah...but double density and 1/10 power consumption would be outstanding for ML type loads...hopefully they can get performance to at least the 1.x GHz range! I'm keeping an eye out...dollars to donuts Cerebras will be using this within a year, once it's qualified for TSMC 5nm.
        nsteel 2y ago
        Not so sure myself. eDRAM has been tried many times and yet here we all are, banging our heads against the SRAM scaling limits. It's such a huge risk for cerebras, they absolutely cannot afford to miss. But then you could say that about a wafer-scale chip...!
throwup238 2y ago
Cerebrus made a great (now deleted) video on the whole computer hosting the wafer: https://web.archive.org/web/20230812020202/https://www.youtube.com/watch?v=pzyZpauU3Ig https://web.archive.org/web/20230812020202/https://www.youtu... It’s fascinating.
- dzhiurgis 2y ago
  TIL - web archive saves youtube videos Wow 200k amps in a chip. Whole thing looks like an early computer from 50s.
- botro 2y ago
  This is a great video, thank you for sharing. My favorite part: "...next we have this rubber sheet, which is very clever, and very patented!"
bigmattystyles 2y ago
How does one cool that!? Heck power it...
tonetegeatinst 2y ago
I'd bet that making a chip the size of the waver has the benefit on not losing any silicon to dicing the wafer up like a desktop or GPU chips coming from a wafer. Major downside is you need to either have a massive x and Y exposure size or break the wafer into smaller exposures which means your still needing to focus on alignment between the steps, and if a defect can't be corrected then is that wafer just scrap?
- throwup238 2y ago
  They fuse off sections of the wafer with defects just like other manufacturers do in monolithic CPUs (as opposed to chiplets like AMD).
idiotsecant 2y ago
Making larger monolithic silicon doesn't get 2x as expensive to get 2x as large. Bigger silicon is massively more expensive. I'm not sure that making each piece require a large chunk of perfect wafer is a fantastic idea, especially when you're looking to unseat juggernauts who have a great deal of experience making high quality product already.
- phonon 2y ago
  It is designed to handle defects. https://www.servethehome.com/cerebras-wafer-scale-engine-ai-chip-is-largest-ever/#:~:text=As%20a%20result%2C%20defects%20are,wires%20to%20handle%20these%20defects https://www.servethehome.com/cerebras-wafer-scale-engine-ai-....
- sitkack 2y ago
  0.5% overheads for defects. You are not correct.

Cerebras is well-known in the AI chip market. They make chips that are an entire wafer. https://spectrum.ieee.org/cerebras-chip-cs3 https://spectrum.ieee.org/cerebras-chip-cs3

alephnerd 2y ago

Yep! Them, SambaNova, and Groq are super exciting mid-late stage startups imo.

Der_Einzige 2y ago
Shhhhh, stop telling the normies about the future! And especially don't tell them to start looking into who "sovereign clouds" actually are!

ericd 2y ago

Interesting that they’ve scaled on-chip memory sublinearly with the growth of transistors between their generations, I would’ve thought they would try to bump that number up. Maybe it’s not a major bottleneck for their training runs?

jrk 2y ago
SRAM is scaling significantly more slowly than logic in recent process nodes.
- ericd 2y ago
  Ahh that explains it, thanks. Seems like a potentially large problem given their strategy.
  - phonon 2y ago
    They could use something like GCRAM[1] to double capacity if they had to...but it's not clear how much worse performance would be. [1]https://raaam-tech.com/products/ https://raaam-tech.com/products/
    - nsteel 2y ago
      The performance doesn't look great (yet). See Fig. 7 https://www.eng.biu.ac.il/fishale/files/2020/12/A-1-Mbit-Fully-Logic-Compatible-3T-Gain-Cell-Embedded-DRAM-in-16-nm-FinFET.pdf https://www.eng.biu.ac.il/fishale/files/2020/12/A-1-Mbit-Ful...
      - phonon 2y ago
        Cerebras runs at 1.1 GHz[1], and this was a much earlier design on 16nm so it might be a good fit by now. Their TSMC 5 nm version is scheduled for early 2025.[2] [1]https://cerebras.ai/blog/cerebras-architecture-deep-dive-first-look-inside-the-hw/sw-co-design-for-deep-learning https://cerebras.ai/blog/cerebras-architecture-deep-dive-fir... [2]https://www.eenewseurope.com/en/raaam-signs-lead-licensee-for-sram-replacement-technology/ https://www.eenewseurope.com/en/raaam-signs-lead-licensee-fo...
        nsteel 2y ago
        They'd have to quadruple their performance to be relevant in the market generally, here's to hoping.
        phonon 2y ago
        Yeah...but double density and 1/10 power consumption would be outstanding for ML type loads...hopefully they can get performance to at least the 1.x GHz range! I'm keeping an eye out...dollars to donuts Cerebras will be using this within a year, once it's qualified for TSMC 5nm.
        nsteel 2y ago
        Not so sure myself. eDRAM has been tried many times and yet here we all are, banging our heads against the SRAM scaling limits. It's such a huge risk for cerebras, they absolutely cannot afford to miss. But then you could say that about a wafer-scale chip...!

throwup238 2y ago

Cerebrus made a great (now deleted) video on the whole computer hosting the wafer: https://web.archive.org/web/20230812020202/https://www.youtube.com/watch?v=pzyZpauU3Ig https://web.archive.org/web/20230812020202/https://www.youtu... It’s fascinating.

dzhiurgis 2y ago
TIL - web archive saves youtube videos Wow 200k amps in a chip. Whole thing looks like an early computer from 50s.
botro 2y ago
This is a great video, thank you for sharing. My favorite part: "...next we have this rubber sheet, which is very clever, and very patented!"

bigmattystyles 2y ago

How does one cool that!? Heck power it...

tonetegeatinst 2y ago

I'd bet that making a chip the size of the waver has the benefit on not losing any silicon to dicing the wafer up like a desktop or GPU chips coming from a wafer. Major downside is you need to either have a massive x and Y exposure size or break the wafer into smaller exposures which means your still needing to focus on alignment between the steps, and if a defect can't be corrected then is that wafer just scrap?

throwup238 2y ago
They fuse off sections of the wafer with defects just like other manufacturers do in monolithic CPUs (as opposed to chiplets like AMD).

idiotsecant 2y ago

Making larger monolithic silicon doesn't get 2x as expensive to get 2x as large. Bigger silicon is massively more expensive. I'm not sure that making each piece require a large chunk of perfect wafer is a fantastic idea, especially when you're looking to unseat juggernauts who have a great deal of experience making high quality product already.

phonon 2y ago
It is designed to handle defects. https://www.servethehome.com/cerebras-wafer-scale-engine-ai-chip-is-largest-ever/#:~:text=As%20a%20result%2C%20defects%20are,wires%20to%20handle%20these%20defects https://www.servethehome.com/cerebras-wafer-scale-engine-ai-....
sitkack 2y ago
0.5% overheads for defects. You are not correct.