4 ms·
Tiny Tapeout VGA Playground
- phendrenad2 2y agoNeat. The example code that makes the cool patterns is here: https://github.com/TinyTapeout/vga-playground/tree/main/src/examples https://github.com/TinyTapeout/vga-playground/tree/main/src/...
- duskwuff 2y agoIt's also in the text editor next to the image, which is editable and affects the image. :) (There's also one bit of shared code in: https://github.com/TinyTapeout/vga-playground/blob/main/src/examples/common/hvsync_generator.v https://github.com/TinyTapeout/vga-playground/blob/main/src/...)
- zokier 2y agoif you like this sort of stuff, tiny tapeout is running a demo competition. i hope we will see some interesting entries there https://tinytapeout.com/competitions/demoscene/ https://tinytapeout.com/competitions/demoscene/
- pengaru 2y agoFor those wondering: Opportunity for new submissions closed Sept. 6th apparently... > 2. Will there be any extension to the deadline? No, it’s September 6th. > 4. When will the competition be judged? 2 weeks after 75% of the boards have been received by entrants (estimated June 2025).
- toivohen 2y agoThere were 32 entries in the competition. The actual competition won't be run until May 2025 or so when the chips are back, but there are already videos of a few of the contributions captured from FPGA or simulation: Drop: https://www.youtube.com/watch?v=jJBU0J2ceMM https://www.youtube.com/watch?v=jJBU0J2ceMM Warp: https://youtu.be/mLHro21KDLE https://youtu.be/mLHro21KDLE Sequential Shadows: https://youtu.be/pkiTu3iLA_U https://youtu.be/pkiTu3iLA_U (version that adheres to the rules starts at 3:08) Demo by a1k0n https://youtu.be/7xPS-0nydms https://youtu.be/7xPS-0nydms
- jmpz 2y agoThis looks like a really fun way to experiment while learning Verilog!
- KallDrexx 2y agoThis is awesome, and I really want to learn enough verilog to do a tiny tape out VGA chip design. But man, 8bitworkshop really burned me out on trying to do verilog in a web IDE, and trying to set up verilator properly for local simulation with a proper IDE became such a hassle. Ended up moving away from verilog for the moment back to normal software projects. I really want to get back in, but I really don't want to spend my limited coding time fighting IDEs and tooling.
- 15155 2y agoTry SpinalHDL or Chisel and never look back.
- KallDrexx 2y agoI was worrying about debuggability if I started with a higher level Verilog transpiler and didn't have a good foundation of Verilog experience. But maybe I should just do it.
- bgnn 2y agoa cheap FPGA kit is the best way to start learning IMHO. Xilinx (now AMD) and Altera (now Intel) free tools are quite good.
- Brusco_RF 2y agoWelcome to Hardware Design! The open-source toolchains come from hell. The closed-source options are supremely expensive and not much better They don't call it EasyWare
- teraflop 2y agoThis looks really cool! A nitpick: the Verilog simulation seems to be handled by the open-source Verilator project, which is packaged as a binary WASM blob without any acknowledgement or source code. I don't think that's compliant with either of the licenses under which Verilator is distributed (LGPL-3.0 or Artistic License). https://github.com/verilator/verilator https://github.com/verilator/verilator
- bgnn 2y agoCool. Reminds me of a course project I did 12 years ago (bacholers..) on an FPGA [1]. I used the ADC on the FPGA board to read the line input audio signal, implemted a VGA driver and a VU meter, implemented a 32-bin FFT to create the VU Meter inputs, and finally implemented a 1 bit delta-sigma modulator to drive a speaker to create the audio back. All in Verilog, on a 100$ FPGA board (Spartan 3 FWIW) in 2 weeks. Good times.. [1] Demo: https://www.youtube.com/watch?v=n3hphFfxZMQ https://www.youtube.com/watch?v=n3hphFfxZMQ