Hmm, this looks like a neat trick to make hardware multiplication faster. Say, for 8-bit numbers it would require 3 8-bit additions/subtractions and one 16-bit

Hmm, this looks like a neat trick to make hardware multiplication faster. Say, for 8-bit numbers it would require 3 8-bit additions/subtractions and one 16-bit addition, one 9-bit shift, and two lookups in a 512-byte table of squares, and zero conditional processing, as opposed to 8 16-bit additione, 8 16-bit shifts, and 8 LSB tests that a naive iterative algorithm would do. I wonder what real integer multiplication hardware uses.