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That's totally nuts. How do they deal with the silicon warping around disabled cores or dark silicon? How long of hard running does it take before the chip ge
by throwawaymaths 2y ago
That's totally nuts. How do they deal with the silicon warping around disabled cores or dark silicon? How long of hard running does it take before the chip gets fatally damaged and needs to be replaced in their system? Word on the street is that h100s fail surprisingly often, this can't be better
- bigcat12345678 2y agohttps://www.youtube.com/watch?v=7GV_OdqzmIU&t=1104s https://www.youtube.com/watch?v=7GV_OdqzmIU&t=1104s This video from Cerebras perfectly explain how they solve the interconnect problem, and why their approach greatly reduces the risk of Blackwell-type hardware design challenges.
- prng2021 2y agoSuper informative video!
- TradingPlaces 2y agoThey have a way of bypassing bad cores, and over-provision both logic and memory by 1.5% to account for that. They get 100% yields this way. https://www.anandtech.com/show/16626/cerebras-unveils-wafer-scale-engine-two-wse2-26-trillion-transistors-100-yield https://www.anandtech.com/show/16626/cerebras-unveils-wafer-...
- throwawaymaths 2y agoYes,that's exactly what would cause the problems I'm suggesting.
- throwup238 2y agoThe way it's mounted, there's unlikely to be warping: https://web.archive.org/web/20230812020202/https://www.youtube.com/watch?v=pzyZpauU3Ig https://web.archive.org/web/20230812020202/https://www.youtu... The cooling is significantly better than what you'd see on a server platform with water cooling channels going to each row of the wafer.
- ChainOfFools 2y agoedit: I should have just checked their website instead of guessing. Apparently WSE has significant fabrication challenges, which makes what Cerebras has accomplished all the more impressive. But it is still surprising that no one else has attempted this in the HPC field. I had guessed that Cerebras had made some trade-offs in process in order to make it work at scale, but then they aren't actually building these devices at scale (yet).
- sanxiyn 2y agoCerebras is known to use TSMC, so your speculation about boutique fab is incorrect. https://cerebras.ai/press-release/cerebras-systems-smashes-the-2-5-trillion-transistor-mark-with-new-second-generation-wafer-scale-engine/ https://cerebras.ai/press-release/cerebras-systems-smashes-t...
- johntb86 2y agoThey're using TSMC 5-nm for WSE-3: https://spectrum.ieee.org/cerebras-chip-cs3 https://spectrum.ieee.org/cerebras-chip-cs3
- throwawaymaths 2y agoIt shouldn't be surprising. It's hard as fuck, and we don't know if it's worth it yet (there's something to be said for "if your compute dies you send your remote hands to swap out a high four figure component" and not "decommission a high-six-figure node"
- ChainOfFools 2y agoI hope I didn't make it sound like it was easy, at least I don't think I said that anywhere. It doesn't really matter how hard something is to do (short of it being trivially proven impossible), it matters whether there's a good enough chance that the payoff exceeds the cost. And actually there have been attempts to do it, I mentioned in an earlier version of my comment that Gene Amdahl had attemped to make WSE work something like 20 years ago, without success - but also without the clear profitability story of AI to attract the same mountains of cash being thrown around today. What's surprising is not that it is hard, or that it's hard as fuck, but that given the potentially stratospheric rewards for success there have not been more attempts in this direction.
- nomel 2y agoIs this all mostly a heat spreader efficiency requirement?
- nomel 2y agoI suppose the proper term would be heat spreader thermal resistance limit, dictated by the thermal stress sums or whatever the term would be.