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ARM or x86? ISA Doesn't Matter (2021)
- Mathnerd314 2y agoSay that when I need to run some program and I have an ARM processor but the only binaries available are x86...
- SG- 2y agowhy would that matter?
- wongarsu 2y agoBoth MacOS and Windows handle that pretty well with JIT, AOT or emulation
- cozzyd 2y agoAnd you can use qemu-user on Linux, though I don't think any distros set it up by default
- makeitdouble 2y agoThis is a valid answer for 90% of people's use. It still kinda makes me sad that the discussion always stops there. It will still break some of whole classes of programs, it's not magic and can either be finicky or just too limited. From the top of my head USB and peripheral access in general is a PITA every time a translation layer is added. Raw device access in emulation never has worked "pretty well". For Mac it wasn't that much of an issue because anyone with deeper hardware needs was probably not there in the first place. But on Windows I'd predict it will be a significant transition pain. A bigger share of people will stick on x86 basically forever to cover their long taily needs.
- olliej 2y agoI’m guessing from your question you did not bother reading the article before commenting. That said this is a solved problem - because plenty of people have arm based machines, and run x86 binaries on them (it obviously comes with a perf cost, but there’s only so much that can be done when dealing with poor engineering)
- jauntywundrkind 2y agoAs a consumer maybe that's true, but as a developer and company making tech, you really can target arm or RISC-V if you care at all and it's not hard at all in a huge number of cases.
- remexre 2y ago> it has got the right top eight instructions that you actually need to optimize for I wonder which ones he considers those to be -- the interview doesn't say, sadly...
- anonymoushn 2y agoI'm hoping we at least get pshufb, aesenc, rep movsb, some sort of integer multiply, and a floating point fma
- janice1999 2y agoThey've made some details public about their architecture [1] and even their RISC-V test suite [2] but I'd also love to know what it was referring to. [1] https://www.theregister.com/2024/08/27/tenstorrent_ai_blackhole/ https://www.theregister.com/2024/08/27/tenstorrent_ai_blackh... [2] https://github.com/tenstorrent/riscv_arch_tests https://github.com/tenstorrent/riscv_arch_tests
- rowanG077 2y agoI would say it's load, store, compare, add, subtract, call, return and branch. If you have that you cover almost all code.
- sgerenser 2y agoImplementing multiplies as a bunch of adds has got to suck for performance though.
- colejohnson66 2y agoWell, if you decompose it to a series of shifts and adds, it’s a bit quicker. That’s actually how the 8086 implemented it.
- rowanG077 2y agoSure. Multiplication is exceedingly rare compared to any of those 8 instructions though. RISC-V base instruction set doesn't include multiplication for example. If you had room to add more then 8 I would rather add the bitops first. This will allow you to also write a much more efficient soft mul in addition to many more things.
- janice1999 2y agoSince Jim Keller is quoted in the article, it would be good to point out that his new company uses RISC-V cores a lot [1] and have licensed their design out [2] to other companies. It seems to have been the correct choice for them. [1] https://www.tomshardware.com/news/tenstorrent-shares-roadmap-of-ultra-high-performance-risc-v-cpus-and-ai-accelerators https://www.tomshardware.com/news/tenstorrent-shares-roadmap... [2] https://www.anandtech.com/show/21281/tenstorrent-licenses-risc-vcpu-ip-to-build-2nm-edge-ai-accelerator https://www.anandtech.com/show/21281/tenstorrent-licenses-ri...
- koito17 2y agoThis paragraph caught my attention This [variable-length coding] is a disadvantage for x86, yet it doesn’t really matter for high performance CPUs ... Why are they leaving out difficilty of building a compiler backend when the ISA has variable-length codes? I would assume an ISA needs to consider its burden on compiler authors. (Itanium is an extreme example of an ISA too tedious for compiler authors) I once extended a Common Lisp compiler to emit machine code for SSE4.2 instructions (specifically minss and maxss). The experience was a bit bad due to subtle differences in prefixes and specific fields needing to be set to activate some mode for SSE4.2 instructions. Now suppose you want to debug a compiler backend targetting x86. Good luck, x86 disassembly is an undeciable problem because you don't know where the instructions start. Meanwhile ARM has two kinds of instructions (full-size and half-size, called "thumb"). Thanks to fixed-length instructions and alignment rules, you always know whether you're in thumb or not. Emitting machine code (and disassembly) is much more straightforward
- mhh__ 2y agoThe amount of code that's being run compiled with systems for which this is a pressing issue is probably ~0%. You're either using an established backend that does all this for you, or realistically you can throw some money at it and make it go away.
- tptacek 2y agoBecause they're not talking about software development cost in the first place.
- pizlonator 2y agoCompilers don’t have to disassemble instructions, so the fact that x86 is hard to disassemble doesn’t matter. And it’s not actually hard in practice if the binary contains labels for function starts. Neither x86 nor arm are easier to compile for, because they both have different quirks that cause headaches. X86 has two operant forms, which require more work. Arm has restrictions on conditional jump distance and immediate encodings, which requires more work. So, an instruction set that had no two operant forms like x86 and that allows any instruction to have any sized immediate would probably be easiest to compile form. Allowing any instruction to have a 32-bit or even 64-bit immediate would lead to either all instructions being huge or to variable length instructions. X86’s use of variable length instructions allows 32-bit immediates everywhere, so in that sense, it makes compiling easier.
- bfung 2y ago> Here in this article we’ll bring together research, comments from people who are very familiar with CPUs, and a bit of our in-house data to show why focusing on the ISA is a waste of time Very amateur-ish question and counterpoint from me: how is Apple M1 performance and power consumption so good compared to the other laptop cpus then?
- xwolfi 2y agoThe code ? Why you think Apple found a way to reverse the heat death of the universe ? They just ... do less stuff so they consume less !
- twoodfin 2y agoApple absolutely leverages their full-stack platform control to optimize their silicon. They know with insane accuracy how many cycles would be saved across a billion phones if they added (say) another integer divide unit, and if they decide that’s worth it, they can rev every major developer’s toolchain to schedule instructions for the new ALU months before the new chip ships.
- saagarjha 2y agoApple doesn’t do this, as it would reveal details about unreleased products. The scheduling model for their CPUs typically drops months after the chips ship, and even then the benefit you get from that is minor. (You can try it yourself, by comparing code generated using the “wrong” microarchitecture versus the “right” one. And also keep in mind that developers don’t always update their apps immediately to use the new toolchain.)
- pizlonator 2y agoSilicon economics mean that whoever has the highest volume can invest the most in better designs and better process. Apple gets volume from the iPhone. This is also why x86 outperformed expensive (and so low volume) RISC workstation CPUs for a long time at single thread perf, and then eventually on multi thread perf too.
- ksec 2y agoMissing [2021] in the title.
- saagarjha 2y agoFixed
- slashdave 2y agoIsn't it kind of obvious that the instruction set itself cannot directly impact performance, since operations are just single clock cycles? I assume the issue is more about the difficulties of implementation, in particular how x86 has a lot of complicated archaic features and corner cases that just absorbs space on silicon, not to mention engineering effort. Apple, being vertically integrated, is free to toss features at will.
- saagarjha 2y agoThis is a pretty simplistic view of how processors execute instructions. They reorder, merge, and speculate execution. Most instructions do not take a single cycle to complete, often they take less or more (and even this depends on how you look at it, since they can be less if you overlap them and more if you look at latency). While this doesn’t mean ISA matters as much as people might think how CPUs work is also more complicated than people might think.
- tiberious726 2y agoWhat synchronous processor can complete an instruction in anything other than a positive integer multiple of its clock?
- slashdave 2y agoIndependent operations can be performed in parallel, with an effective throughput of a fraction of a clock. However, this is not something that depends on instruction set.
- crest 2y agoThe ISA can massively impact performance on relevant real-world workloads, but the divide isn't along the mythical RISC vs. CISC divide. Take H.264 encoding as a contrived example and try it with different x86 ISA levels (e.g. no SIMD vs. SSE2 vs. SSE4.2 vs. AVX256 vs. AVX-512 on the same Zen 5 desktop CPU. You can't just build a 32-wide OoO core and have it run at a useful clock speed.
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- jovial_cavalier 2y agoSo... why doesn't Intel "just" make a low-power x86 processor and win everything forever?
- Topfi 2y agoOne could argue that Lunar Lake is exactly that. At least, it and arguably AMDs monolithic mobile SOCs starting with Zen 2 have shown that one can be competitive in terms of efficiency with ARM equivalents. The 4800U and M2 were more closely matched than I feel many in the media gave them credit for. Lunar Lake now appears more than competitive in that regard with even the higher end M3 SKUs, though of course M4 Pro and Max are around the corner. Apple, more than the ARM ISA, seems responisble for the prevailing impression that ARM is inherently more efficient because Apple were simply the first to put such major investment into targeting specifically mobile SKUs, rather than scaling down from server focused products. Snapdragon X showcases that quite impressively, ARM based but efficiency wise Apple, Intel and AMD SKUs appear more competitive.
- herdonbesecker 2y ago[dead]
- howtofly 2y ago[dead]
- freitzkriesler2 2y ago[dead]
- CalChris 2y agoIf ISAs really didn't matter then Apple would have switched horses.
- snvzz 2y agoIf ISA really does not matter, then RISC-V is a no-brainer, due to its licensing.