4 ms·
This is a consequence of not specifying that an encoding should lead to a fault. It isn't that the instruction is faulty, it is that the instruction doesn't ex
by sitkack 2y ago
This is a consequence of not specifying that an encoding should lead to a fault. It isn't that the instruction is faulty, it is that the instruction doesn't exist and still triggers an action. Yes it is semantics, but a distinction worth noting.
https://old.reddit.com/r/RISCV/comments/1emhhzs/alibabas_thead_c910_riscv_chips_blow_away_all/ https://old.reddit.com/r/RISCV/comments/1emhhzs/alibabas_the...
- duskwuff 2y agoI don't think that's accurate. These vector instructions are defined (by the vendor) and were intended to be accessible; the problem is that they have unexpected and insecure behavior.
- dzaima 2y agoThe instruction in question doesn't map to any instruction in neither RVV0.7.1/xtheadvector, nor RVV1.0. Disassemblers don't disassemble it, and assemblers don't have any mnemonic for it (the 'vse128.v' used by the authors is essentially arbitrary afaict; and even if it weren't, there's zero reason to think that C910 had any intention of supporting 128-bit elements)