4 ms·

> The current densest NAND uses 16 different positive voltage states to encode 4 bits per cell. Wait, what?! I did not know this. Is there a link where I can

by breck 2y ago

> The current densest NAND uses 16 different positive voltage states to encode 4 bits per cell. Wait, what?! I did not know this. Is there a link where I can learn more?

p1mrx 2y ago
https://en.wikipedia.org/wiki/Multi-level_cell https://en.wikipedia.org/wiki/Multi-level_cell
- breck 2y ago
  Very interesting. I would have thought the overhead from the memory controller would negate all savings, but I know very little about modern cell design.
  - marcosdumay 2y ago
    > overhead from the memory controller If you want to do it in a single step, you need 8 analogic comparators at the output of the memory, and one level of "and" and "or" gates to solve each bit. Most ADCs use a single comparator + OpAmp and convert the value in 3 steps. But that would make your memory slower. Either way, the task of converting it does not fall over the controller.
jsheard 2y ago
https://www.anandtech.com/show/5067/understanding-tlc-nand https://www.anandtech.com/show/5067/understanding-tlc-nand That's an older article from when TLC (3bit) NAND launched, but the principles are the same for QLC (4bit). Nowadays SLC and MLC are barely used because TLC is good enough for nearly all purposes.
- breck 2y ago
  > Nowadays SLC and MLC are barely used because TLC is good enough for nearly all purposes. This is very interesting. Thank you.
- AlotOfReading 2y ago
  Most "SLC" and "MLC" that's sold is actually TLC/QLC hardware that's only using a subset of the voltage levels available. It ends up being significantly cheaper due to the economies of scale in manufacturing.
  - jsheard 2y ago
    Yep, if you ever come accross the term "pSLC" (Pseudo-SLC) that means the underlying hardware is capable of running in MLC/TLC/QLC mode, but the controller firmware has been configured to only use the lowest and highest voltage state in each cell. Some SSD controllers will also reassign regions of flash to different modes on the fly, the drives unused capacity can be used internally as a very fast pSLC write cache, and then as the drive fills up those cells incrementally get switched over to the native TLC/QLC mode.
    - Iulioh 2y ago
      Does this mean that in some cases damaged QCL "sectors" could be still used as a SCL?

by breck 2y ago

> The current densest NAND uses 16 different positive voltage states to encode 4 bits per cell. Wait, what?! I did not know this. Is there a link where I can learn more?

p1mrx 2y ago

https://en.wikipedia.org/wiki/Multi-level_cell https://en.wikipedia.org/wiki/Multi-level_cell

breck 2y ago
Very interesting. I would have thought the overhead from the memory controller would negate all savings, but I know very little about modern cell design.
- marcosdumay 2y ago
  > overhead from the memory controller If you want to do it in a single step, you need 8 analogic comparators at the output of the memory, and one level of "and" and "or" gates to solve each bit. Most ADCs use a single comparator + OpAmp and convert the value in 3 steps. But that would make your memory slower. Either way, the task of converting it does not fall over the controller.

jsheard 2y ago

https://www.anandtech.com/show/5067/understanding-tlc-nand https://www.anandtech.com/show/5067/understanding-tlc-nand That's an older article from when TLC (3bit) NAND launched, but the principles are the same for QLC (4bit). Nowadays SLC and MLC are barely used because TLC is good enough for nearly all purposes.

breck 2y ago
> Nowadays SLC and MLC are barely used because TLC is good enough for nearly all purposes. This is very interesting. Thank you.
AlotOfReading 2y ago
Most "SLC" and "MLC" that's sold is actually TLC/QLC hardware that's only using a subset of the voltage levels available. It ends up being significantly cheaper due to the economies of scale in manufacturing.
- jsheard 2y ago
  Yep, if you ever come accross the term "pSLC" (Pseudo-SLC) that means the underlying hardware is capable of running in MLC/TLC/QLC mode, but the controller firmware has been configured to only use the lowest and highest voltage state in each cell. Some SSD controllers will also reassign regions of flash to different modes on the fly, the drives unused capacity can be used internally as a very fast pSLC write cache, and then as the drive fills up those cells incrementally get switched over to the native TLC/QLC mode.
  - Iulioh 2y ago
    Does this mean that in some cases damaged QCL "sectors" could be still used as a SCL?