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This seems like a great way to test the waters before a potential full-on transition to RISC-V. It allows to validate both technically and market reception, for

This seems like a great way to test the waters before a potential full-on transition to RISC-V. It allows to validate both technically and market reception, for a much lower cost than taping out a additional chip.

MBCook 2y ago
Fun for benchmarking too. You’re limited to those two exact kinds of cores, but you know every other thing on the entire computer is 100% identical. It’s not SBC 1 vs SBC 2, but they have different RAM chips and this one has a better cooler but that one better WiFi.
- phire 2y ago
  I really hope people don't do this. Or at least not try to sell it as ARM vs RISC-V tests. Because what you are really testing is the Cortex-M33 vs the Hazard 3, and they aren't equivalent. They might both be 3 stage in-order RISC pipelines, but Cortex-M33 is technically superscalar, as it can dual-issue two 16bit instructions in certain situations. Also, the Cortex-M33 has a faster divider, 11 cycles with early termination vs 18 or 19 cycles on the Hazard 3.
  - snvzz 2y ago
    It'd help to know how much area each core takes within the die. I would expect the ARM cores to be much larger, as well as use much more power.
    - phire 2y ago
      Hard to tell. If you ignore the FPU (I think it can be power gated off) the two cores should be roughly the same size and power consumption. Dual issue sounds like it would add a bunch of complexity, but ARM describe it as "limited" (and that's about all I can say, I couldn't find any documentation). The impression I get is that it's really simple. Something along the line of "if two 16 bit instructions are 32bit aligned, and they go down different pipelines, and they aren't dependant on each other" then execute both. It might be limitations that the second instruction can't access registers at all (for example, a branch instruction) or that it must only access registers from seperate register file bank, meaning you don't even have to add extra read/write ports to the register file. If the feature is limited enough, you could get it down to just a few hundred gates in the instruction decode stage, taking advantage of resources in later stages that would have otherwise been idle. According to ARM's specs, the Cortex-M33 takes the exact same area as the Cortex-M4 (the rough older equivalent without dual-issue, and arguably equal to the Hazard3), uses 2.5% less power and gets 17% more performance in the CoreMark benchmark.
      - pclmulqdq 2y ago
        That is exactly what the "limited dual issue" is - two non-conflicting pre-decoded instructions (either 16b+16b or if a stall has occurred) can be sent down the execution pipe at the same time. I believe that must be a memory op and an ALU op.
    - KaiserPro 2y ago
      The ARM cores are probably much larger, but I don't think that translates into better power efficiency _automatically_.
GordonS 2y ago
My thoughts exactly - a risc-free (hurhur) way to get RISC-V in the hands of many, many devs.
kelnos 2y ago
I do wonder if the unavailability of some of the security features and -- possibly a big deal for some applications -- the accelerated floating point on the RISC-V cores would skew that experiment, though.
askvictor 2y ago
Indeed, though I'm curious about the rationale behind it. It is a 'plan B' in case their relationship with ARM sours? It is aiming for cost-cutting in the future (I can't imagine the ARM licences are costing them much given the price of the RP2040, but maybe they're absorbing it to get marketshare)
- snvzz 2y ago
  Embracing RISC-V, the high-quality open-source ISA that is rapidly growing the strongest ecosystem, does make a lot of sense.

MBCook 2y ago

Fun for benchmarking too. You’re limited to those two exact kinds of cores, but you know every other thing on the entire computer is 100% identical. It’s not SBC 1 vs SBC 2, but they have different RAM chips and this one has a better cooler but that one better WiFi.

phire 2y ago
I really hope people don't do this. Or at least not try to sell it as ARM vs RISC-V tests. Because what you are really testing is the Cortex-M33 vs the Hazard 3, and they aren't equivalent. They might both be 3 stage in-order RISC pipelines, but Cortex-M33 is technically superscalar, as it can dual-issue two 16bit instructions in certain situations. Also, the Cortex-M33 has a faster divider, 11 cycles with early termination vs 18 or 19 cycles on the Hazard 3.
- snvzz 2y ago
  It'd help to know how much area each core takes within the die. I would expect the ARM cores to be much larger, as well as use much more power.
  - phire 2y ago
    Hard to tell. If you ignore the FPU (I think it can be power gated off) the two cores should be roughly the same size and power consumption. Dual issue sounds like it would add a bunch of complexity, but ARM describe it as "limited" (and that's about all I can say, I couldn't find any documentation). The impression I get is that it's really simple. Something along the line of "if two 16 bit instructions are 32bit aligned, and they go down different pipelines, and they aren't dependant on each other" then execute both. It might be limitations that the second instruction can't access registers at all (for example, a branch instruction) or that it must only access registers from seperate register file bank, meaning you don't even have to add extra read/write ports to the register file. If the feature is limited enough, you could get it down to just a few hundred gates in the instruction decode stage, taking advantage of resources in later stages that would have otherwise been idle. According to ARM's specs, the Cortex-M33 takes the exact same area as the Cortex-M4 (the rough older equivalent without dual-issue, and arguably equal to the Hazard3), uses 2.5% less power and gets 17% more performance in the CoreMark benchmark.
    - pclmulqdq 2y ago
      That is exactly what the "limited dual issue" is - two non-conflicting pre-decoded instructions (either 16b+16b or if a stall has occurred) can be sent down the execution pipe at the same time. I believe that must be a memory op and an ALU op.
  - KaiserPro 2y ago
    The ARM cores are probably much larger, but I don't think that translates into better power efficiency _automatically_.

GordonS 2y ago

My thoughts exactly - a risc-free (hurhur) way to get RISC-V in the hands of many, many devs.

kelnos 2y ago

I do wonder if the unavailability of some of the security features and -- possibly a big deal for some applications -- the accelerated floating point on the RISC-V cores would skew that experiment, though.

askvictor 2y ago

Indeed, though I'm curious about the rationale behind it. It is a 'plan B' in case their relationship with ARM sours? It is aiming for cost-cutting in the future (I can't imagine the ARM licences are costing them much given the price of the RP2040, but maybe they're absorbing it to get marketshare)

snvzz 2y ago
Embracing RISC-V, the high-quality open-source ISA that is rapidly growing the strongest ecosystem, does make a lot of sense.