3 ms·
this doesn't seem to reflect the reality of the way hardware is actually being added to the cores, where Zen5 features a fourth ALU which is only useful to a si
by paulmd 2y ago
this doesn't seem to reflect the reality of the way hardware is actually being added to the cores, where Zen5 features a fourth ALU which is only useful to a single thread in the low-single-digits.
https://old.reddit.com/r/hardware/comments/1ee7o1d/the_amd_ryzen_ai_9_hx_370_review_unleashing_zen_5/lfcnnjs/ https://old.reddit.com/r/hardware/comments/1ee7o1d/the_amd_r...
this isn't adding more units to speed up single-thread and SMT being a nice "incidental" gain, this is actively targeting wide architectures that have lots of pipeline bubbles for SMT to fill.
and that's fine, but it's also a very different dynamic than, eg, apple silicon, where the focus is running super deep speculation and reordering on a single thread.
- Dylan16807 2y agoWhat do you think they should add instead of another ALU? The returns are diminishing, but a single digit bump is still a pretty good when your goal is faster single threads. Adding nothing to save space is obviously not the answer, because that leads to having more slower cores. Also the topic of the post, the 2-ahead branch predictor, exists specifically to get more ALUs running in parallel! > apple silicon, where the focus is running super deep speculation And to make that speculation profitable, the M1 cores have 6 ALUs among other wideness.