3 ms·
The article says the chips are made on a 180 nm process and they come out about the size of a table salt grain. We’re now down in the single digits for fabrica
by MBCook 2y ago
The article says the chips are made on a 180 nm process and they come out about the size of a table salt grain.
We’re now down in the single digits for fabrication in nanometers, although I know that sort of just a name. This chip is so tiny already, if you were to fab it on a process like 7 nm I’m guessing it would be unworkably small. Too hard to cut, too hard to manipulate individual chips once you did manage to cut them.
So here’s my question: how small can we make a chip in area while still being able to cut them out and easily use them?
It’s obviously not a concern for the hundreds of square millimeters of a large processor, but I’ve never heard about the opposite end of the spectrum before.
- kens 2y agoThere are a few issues. First, you lose 20 µm due to the saw cut between the dies. I saw an NXP patent that said this was wasting 30% of the die for their tiny chips. If you made the chips smaller, you'd be wasting even more. Another issue is that you need some area for the bond pads, so you can't make your chips arbitrarily small or they will be useless. Looking at a random die pick-and-place machine [1], it handles dies down to 0.2mm in either dimension. So you could handle smaller dies than mine with an off-the-shelf machine, but not a lot smaller. [1] The video of the die machine in action is pretty cool: https://www.syagrussystems.com/dts-2-die-sorter https://www.syagrussystems.com/dts-2-die-sorter
- MBCook 2y ago0.2mm per side? Wow that’s smaller than I’d expect. Thanks. The increased losses due to cutting make sense too. I was expecting the cuts to be wider than 20 µm, so that’s not actually as bad as I was imagining.