5 ms·

Syzygy: An open standard for low cost, compact and high-performance peripherals

133 points by teleforce 2y ago

codevark 2y ago
[dead]
stn8188 2y ago
Oh wow, I forgot about this. Syzygy was supposed to be like PMOD but higher speed capabilities. I actually put it into a design, but never got around to fabricating it. https://forums.sifive.com/t/friscy-new-high-performance-pcb-coming-with-fe310-fpga-suitable-for-development-or-production-systems/962 https://forums.sifive.com/t/friscy-new-high-performance-pcb-... (Warning, hyperlinks are definitely gonna be broken from that post). I wonder how popular the interface has been over the last few years - I haven't really paid attention.
- duskwuff 2y ago
  It hasn't really taken off beyond Digilent. Xilinx still uses FMC/FMC+, Altera/Intel/Altera still uses HSMC.
emusan 2y ago
Hadn’t expected to see this here! I helped put this standard together while working at Opal Kelly. I think we had some nifty ideas in there (using an analog voltage for peripheral addressing was one of my favorite). It has slowly seen more adoption as time passes. Would always love to see more adoption!
- slyfox125 2y ago
  That sounds interesting (analog addressing). Could you expound?
  - emusan 2y ago
    With many of these types of standards (FMC and Syzygy) it becomes helpful to include some form of memory on the peripheral cards. With Syzygy it is required in order to store some helpful data about the card (product name, manufacturer) along with supported voltage ranges for an adjustable voltage rail from the carrier board. FMC used standard off the shelf I2C eeproms for this task, with some pins on the FMC connector used to indicate the address for the particular slot that the peripheral was attached to on the motherboard. We wanted to lose as few pins as possible for address lines on Syzygy, so we opted to instead use a microcontroller with an ADC for our peripheral flash memory. There was a single pin used to indicate the peripheral address. This pin had a fixed resistor to a power rail on the peripheral and the carrier would have a port-specific resistor to ground on the same pin. By reading the voltage across these resistors we defined 16 addresses with just a single pin. IIRC the microcontrollers we selected were almost the same cost as the I2C flash we would have used in their place! It was a pretty neat hack. Placing small microcontrollers on the peripherals also opened up other functions like using them for basic power supply sequencing.
    - slyfox125 2y ago
      Thank you for the explanation. Very interesting!
iAkashPaul 2y ago
I remember watching Andy Barry/MIT demo of Pushbroom stereo approach on a flying-wing drone, it used stereo 120FPS cameras to dodge trees & branches. It's almost a decade later now & such hardware is still not cheaply available for Pi's/SBCs.
jpm_sd 2y ago
I'm not familiar with the other standards this is being compared to. Why not use PCIe?
- dist-epoch 2y ago
  I think you missed the "low-cost" part from the title.
  - Twirrim 2y ago
    Why is PCIe expensive?
    - bobmcnamara 2y ago
      I suspect part of it is the serdes.
- Neywiny 2y ago
  2 primary reasons come to mind: 1. PCIe is mostly transceivers. Syzygy can be low speed, single ended, etc etc as well. 2. PCIe's card edge connectors can add manufacturing cost (gold plating, chamfered edges, board thickness tricks, etc) and are also relatively large.
  - jpm_sd 2y ago
    PCIe doesn't have to be over an edge connector. PMC and XMC standards use board-to-board stacking. You can also do PCIe over cabling. What's the point of low speed single ended I/O into an FPGA module? Seems like a waste of effort.
    - bobmcnamara 2y ago
      > What's the point of low speed single ended I/O into an FPGA module? Hardware interfacing with the physical world. Driving small numbers of LEDs, h-bridge drivers, load switches, regulator control signals, reading buttons, accelerometers, gyroscopes, magnetometers, PWM controllers, GPS, ...
webdevver 2y ago
random rant not really related to op but spurred by it: i know it will probably never happen, but it would be 'truly epic' if hard PCIe endpoints became as ubiquitous as say, SPI peripheral blocks, within MCUs/MPUs and the general silicon jelly-bean world. just a very high speed, very low latency, very widespread, very standard, very boring communication channel. and ofcourse an atmega328p can't keep up with the full b/w, but even something like an rp2040 could take serious advantage of such a fast port. it would mean that fast information interchange would be available for "anyone", and most importantly, could be interfaced with a bog-standard run of the mill desktop PC. it feels like, right now, if you want to do pcie stuff you have to either go FPGA, which seem like theyre quite far behind: artix stuff is pcie gen 2, i think gowin announced some pcie4 products but im not sure if they ever became real - and fpgas ofcourse are expensive and drag in a bunch of other considerations that you may not want or may be detrimental to your project... or go for a limited selection of (often closed source) mcus/mpus, thankfully the raspberry pi isnt that closed, but if the rpi doesnt have what you want then you have to go for say a rockchip, or whatever asian SOC that often has a very ambivalent relationship with datasheet availability. and even then they might not support operating the pcie in device mode (might be misremembering) whatever, maybe im talking rubbish. i remember wanting to make some kind of USB3 gadget and being incredibly frustrated that the only option among the ocean of MCUs was the cypress ezkit bridged to a parallel bus to an FPGA. so lame! i think xilinx offered a usb3 peripheral IP block but it was behind an expensive license. i think since then there have become available USB3-capable RISC-V MCUs, thankfully, but im still surprised that nobody seems to really care about fast low latency data transfer. i guess its just not very important for "real" applications out in the wild.
- Neywiny 2y ago
  I'm hoping UCIe starts to fix this. It's touted as being something that can combine the low power with the high speed. As is PCIe is a relatively high power for anything that doesn't need the speed. You need to be moving pretty well past normal MCU interfaces (spi, uart, etc) before you see the power trade off. As is, PCIe would add sizable die area consumption, raise power consumption by an order of magnitude, and likely raise part cost dramatically. Couple this with cheapy board designs that often can't even get USB 1.0-2.0 right (recalling the amount of boards that get the pull up resistors or power supply schema wrong), and it sounds like a nightmare to manage. I think gigabit Ethernet is where I'd prefer the effort spent. Most micros have at most 100 Mb. NXP's i.MX RT line has gigabit but that's the only one I know of.
jauntywundrkind 2y ago
Syzygy imo largely failed to be adopted because microcontrollers (& app processors) haven't improved all that much. We are barely seeing a lane or two of pcie 2 appear. I am just aghast at how slow so much of the computing world moves. Cortex A53 is twelve years old, & still rampantly abundant & the go to option, or it's barely improved at all A55. We still see lots of A7's too for lower power, only barely beginning to be replaced by A32. The M7 has been a significant boost but the M3/4 are enduring. ADC/DAC have gotten a bit better for microcontrollers, but we are so far away from bandwidth & connectivity being competed on, being competitive. This was a more hopeful future.
- datameta 2y ago
  Recalibrate your weights toward more recent developments (post '21) and you will see a clearer picture, I think. M7 is quite popular now for TinyML applications (600MHz for an MCU!!). It's somewhere between RPi 2 and 3 based on Core Mark score and what I've seen in terms of CV capabilities. Things are moving very fast imo. MCUs can do 1080p at 30fps now and not just from faster hardware but with some impressive additions to instruction sets! Edit: After re-reading I see that you're talking about adoption rates, in which case, fair points.
- pclmulqdq 2y ago
  The real reason seems to be that FMC has basically won this socket, not that MCUs/MPUs aren't powerful enough. FMC is bigger, but it's also a lot more flexible.

133 points by teleforce 2y ago

[dead]

Oh wow, I forgot about this. Syzygy was supposed to be like PMOD but higher speed capabilities. I actually put it into a design, but never got around to fabricating it. https://forums.sifive.com/t/friscy-new-high-performance-pcb-coming-with-fe310-fpga-suitable-for-development-or-production-systems/962 https://forums.sifive.com/t/friscy-new-high-performance-pcb-... (Warning, hyperlinks are definitely gonna be broken from that post). I wonder how popular the interface has been over the last few years - I haven't really paid attention.

duskwuff 2y ago
It hasn't really taken off beyond Digilent. Xilinx still uses FMC/FMC+, Altera/Intel/Altera still uses HSMC.

emusan 2y ago

Hadn’t expected to see this here! I helped put this standard together while working at Opal Kelly. I think we had some nifty ideas in there (using an analog voltage for peripheral addressing was one of my favorite). It has slowly seen more adoption as time passes. Would always love to see more adoption!

slyfox125 2y ago
That sounds interesting (analog addressing). Could you expound?
- emusan 2y ago
  With many of these types of standards (FMC and Syzygy) it becomes helpful to include some form of memory on the peripheral cards. With Syzygy it is required in order to store some helpful data about the card (product name, manufacturer) along with supported voltage ranges for an adjustable voltage rail from the carrier board. FMC used standard off the shelf I2C eeproms for this task, with some pins on the FMC connector used to indicate the address for the particular slot that the peripheral was attached to on the motherboard. We wanted to lose as few pins as possible for address lines on Syzygy, so we opted to instead use a microcontroller with an ADC for our peripheral flash memory. There was a single pin used to indicate the peripheral address. This pin had a fixed resistor to a power rail on the peripheral and the carrier would have a port-specific resistor to ground on the same pin. By reading the voltage across these resistors we defined 16 addresses with just a single pin. IIRC the microcontrollers we selected were almost the same cost as the I2C flash we would have used in their place! It was a pretty neat hack. Placing small microcontrollers on the peripherals also opened up other functions like using them for basic power supply sequencing.
  - slyfox125 2y ago
    Thank you for the explanation. Very interesting!

iAkashPaul 2y ago

I remember watching Andy Barry/MIT demo of Pushbroom stereo approach on a flying-wing drone, it used stereo 120FPS cameras to dodge trees & branches. It's almost a decade later now & such hardware is still not cheaply available for Pi's/SBCs.

jpm_sd 2y ago

I'm not familiar with the other standards this is being compared to. Why not use PCIe?

dist-epoch 2y ago
I think you missed the "low-cost" part from the title.
- Twirrim 2y ago
  Why is PCIe expensive?
  - bobmcnamara 2y ago
    I suspect part of it is the serdes.
Neywiny 2y ago
2 primary reasons come to mind: 1. PCIe is mostly transceivers. Syzygy can be low speed, single ended, etc etc as well. 2. PCIe's card edge connectors can add manufacturing cost (gold plating, chamfered edges, board thickness tricks, etc) and are also relatively large.
- jpm_sd 2y ago
  PCIe doesn't have to be over an edge connector. PMC and XMC standards use board-to-board stacking. You can also do PCIe over cabling. What's the point of low speed single ended I/O into an FPGA module? Seems like a waste of effort.
  - bobmcnamara 2y ago
    > What's the point of low speed single ended I/O into an FPGA module? Hardware interfacing with the physical world. Driving small numbers of LEDs, h-bridge drivers, load switches, regulator control signals, reading buttons, accelerometers, gyroscopes, magnetometers, PWM controllers, GPS, ...

webdevver 2y ago

random rant not really related to op but spurred by it: i know it will probably never happen, but it would be 'truly epic' if hard PCIe endpoints became as ubiquitous as say, SPI peripheral blocks, within MCUs/MPUs and the general silicon jelly-bean world. just a very high speed, very low latency, very widespread, very standard, very boring communication channel. and ofcourse an atmega328p can't keep up with the full b/w, but even something like an rp2040 could take serious advantage of such a fast port. it would mean that fast information interchange would be available for "anyone", and most importantly, could be interfaced with a bog-standard run of the mill desktop PC. it feels like, right now, if you want to do pcie stuff you have to either go FPGA, which seem like theyre quite far behind: artix stuff is pcie gen 2, i think gowin announced some pcie4 products but im not sure if they ever became real - and fpgas ofcourse are expensive and drag in a bunch of other considerations that you may not want or may be detrimental to your project... or go for a limited selection of (often closed source) mcus/mpus, thankfully the raspberry pi isnt that closed, but if the rpi doesnt have what you want then you have to go for say a rockchip, or whatever asian SOC that often has a very ambivalent relationship with datasheet availability. and even then they might not support operating the pcie in device mode (might be misremembering) whatever, maybe im talking rubbish. i remember wanting to make some kind of USB3 gadget and being incredibly frustrated that the only option among the ocean of MCUs was the cypress ezkit bridged to a parallel bus to an FPGA. so lame! i think xilinx offered a usb3 peripheral IP block but it was behind an expensive license. i think since then there have become available USB3-capable RISC-V MCUs, thankfully, but im still surprised that nobody seems to really care about fast low latency data transfer. i guess its just not very important for "real" applications out in the wild.

Neywiny 2y ago
I'm hoping UCIe starts to fix this. It's touted as being something that can combine the low power with the high speed. As is PCIe is a relatively high power for anything that doesn't need the speed. You need to be moving pretty well past normal MCU interfaces (spi, uart, etc) before you see the power trade off. As is, PCIe would add sizable die area consumption, raise power consumption by an order of magnitude, and likely raise part cost dramatically. Couple this with cheapy board designs that often can't even get USB 1.0-2.0 right (recalling the amount of boards that get the pull up resistors or power supply schema wrong), and it sounds like a nightmare to manage. I think gigabit Ethernet is where I'd prefer the effort spent. Most micros have at most 100 Mb. NXP's i.MX RT line has gigabit but that's the only one I know of.

jauntywundrkind 2y ago

Syzygy imo largely failed to be adopted because microcontrollers (& app processors) haven't improved all that much. We are barely seeing a lane or two of pcie 2 appear. I am just aghast at how slow so much of the computing world moves. Cortex A53 is twelve years old, & still rampantly abundant & the go to option, or it's barely improved at all A55. We still see lots of A7's too for lower power, only barely beginning to be replaced by A32. The M7 has been a significant boost but the M3/4 are enduring. ADC/DAC have gotten a bit better for microcontrollers, but we are so far away from bandwidth & connectivity being competed on, being competitive. This was a more hopeful future.

datameta 2y ago
Recalibrate your weights toward more recent developments (post '21) and you will see a clearer picture, I think. M7 is quite popular now for TinyML applications (600MHz for an MCU!!). It's somewhere between RPi 2 and 3 based on Core Mark score and what I've seen in terms of CV capabilities. Things are moving very fast imo. MCUs can do 1080p at 30fps now and not just from faster hardware but with some impressive additions to instruction sets! Edit: After re-reading I see that you're talking about adoption rates, in which case, fair points.
pclmulqdq 2y ago
The real reason seems to be that FMC has basically won this socket, not that MCUs/MPUs aren't powerful enough. FMC is bigger, but it's also a lot more flexible.