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Eh, the Cell would have been a fantastic processor if it weren't for hitting the end of dennard scaling like a brick wall. In the design phase they were expect
by monocasa 2y ago
Eh, the Cell would have been a fantastic processor if it weren't for hitting the end of dennard scaling like a brick wall.
In the design phase they were expecting almost 5ghz at launch, and to hit around 10ghz at the end of the product lifecycle. When the process guys came back later to let the architects know the reality we've sort of now all internalized (high end consumer electronics can expect ~3ghz with good cooling solutions) a lot of simple but fast pipeline designs stopped making sense. These are the exact same pressures that killed off the Netburst architecture too, making intel go back to a PIII design and make it smarter rather than clock markedly faster.
- wmf 2y agoNah, SPEs are a bad idea at any frequency.
- monocasa 2y agoWhat specifically about them?
- wmf 2y agoMostly not having caches.
- bobmcnamara 2y agoThe TCMs were cool. But unless your work fits that...
- corysama 2y agoThe SPEs only had cache! (And, a ton of registers.) What they were missing was RAM ;D But, even that wasn’t as bad as it was made out to be. People rightly moan about the awkwardness of asynchronously moving data between main RAM and the SPE memory. What they don’t often mention is that the latency of those moves was about 500 cycles —the same latency as a cache miss on the PPE CPUs! So, which was worse: implicitly waiting 500 cycles all over the place? Or, explicitly scheduling 500 cycle waits at specific points? Unsurprisingly, everyone preferred the first option :P
- rbanffy 2y agoNothing prevents them from having their own RAM - ISAs and implementations can be extended. The market for the Cell never materialised in the end, but it could have turned into something a lot more interesting.