10 ms·
The most annoying part about the PIO is that there are only two of them (though with 4 sub-units each), they only have space for 32 instructions, and they don't
by crote 2y ago
The most annoying part about the PIO is that there are only two of them (though with 4 sub-units each), they only have space for 32 instructions, and they don't have an external clock input.
They are great for implementing very basic peripherals, but more than once I've started to implement something more complex just to realize it would be unacceptably slow and run out of space. If they were to beef them up just a little, they could easily replace the more trivial FPGA applications.
- 15155 2y agoAdd a $2.80 ICE40 with built-in NVM and your problems are solved.
- crote 2y agoConsidering the RP2040 is only $0.70, not exactly an attractive option.
- 15155 2y agoIf an RP2040 doesn't fit the task because it has a pitiful amount of IO, you're now into using two anyway. Two chips, two SPI flashes, two crystals - likely more than the FPGA. If it matters for the task, that FPGA will be able to achieve nanosecond-order IO/clock-to-clock skew times - PIO is painfully bad at this (and is executed serially.) If the task will fit FlexIO's restrictions, the NXP IMXRT1011 at $1.70 blows away the $0.70 RP2040 in basically every metric.