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A trustworthy, free (libre), Linux capable, self-hosting 64bit RISC-V computer
- buildbot 2y agoIt’s really quite amazing to login a linux shell on an orangecrab FPGA running a RISV-V softcore, built using an open source toolchain. That was impossible not so long ago! At best you’d have something like Xilinx PetaLinux and all their proprietary junk.
- 3abiton 2y agoThis is and will be a rallying moment soon for the community, both open hardware and software finally working together! This will be huge by the end of the decade.
- taftster 2y agoI guess using some local definition of "huge".
- almostgotcaught 2y ago> This is and will be a rallying moment soon for the community My guy this thing is 4 years old. Spoiler alert: it wasn't.
- snvzz 2y agoFun thing is that orangecrab's FPGA is not even a requirement. A tiny iCE40 LP1K will fit SERV (and even QERV) no prob. It's amazing how small a fully compliant RISC-V implementation can be.
- Guestmodinfo 2y agoWow, I am starting to read all your reading material that you have put up. It's really what I have always wanted to do and it's more than that because you are using FPGAs. I am from India and I want to help you in any way I can because I also have wanted to go on this journey. It's just amazing I wish you all the blessings.
- dmarinus 2y agohey this is the same guy who did some work for running osx on qemu/kvm. https://www.contrib.andrew.cmu.edu/~somlo/OSXKVM/ https://www.contrib.andrew.cmu.edu/~somlo/OSXKVM/
- bitcompost 2y agoWhile I love the idea of self-hosting HW and SW, I can't even imagine the pain of building stuff like GCC on 60Mhz CPU. Not to mention the Rocket CPU is written in Scala. I recently stopped using Gentoo on RockPro64, because the compile times were unbearable, and that's a system orders of magnitude faster than what they want to use.
- shrubble 2y agoPeople used 50Mhz SPARC systems to do real work, and the peripherals were all a lot slower (10mbps Ethernet, slower SCSI drives) with less and slower RAM. But it might take a week to compile everything you wanted, I agree; of course there is always cross-compiling as well.
- bitcompost 2y agoOh I believe in theory a 50Mhz CPU is capable of doing almost everything I need, but it just lacks the software optimized for it. I think a week to compile everything is too optimistic.
- kwhitefoot 2y agoI did valuable work on a 2 MHz Apple II with a 4 MHz Z80 add-on running CP/M that I used to write the documentation. The documentation part was just as fast forty years ago as it is now but assembling the code was glacially slow. The 6502 macro assembler running on the Apple too forty minutes to assemble code that filled an 8 k EPROM.
- musicale 2y ago6502 assemblers are amazingly fast on more recent hardware. Something like 60-70ms to run a script to assemble and link an a version of msbasic (AppleSoft) on my old laptop. https://github.com/mist64/msbasic https://github.com/mist64/msbasic
- 2y ago
- robinsonb5 2y agoThis is very, very cool. I've been thinking for a while that a fully self-hosted RISC-V machine is sorely needed. The biggest limiting factor at the moment actually seems to be finding an FPGA board which has enough RAM on board. The target board here has 512 megabytes, I think - but FPGA toolchains are much happier with several gigabytes to play with.
- amelius 2y ago> The chip foundry wouldn't know what the FPGA will be used for, and where the proverbial "privilege bit" will end up being laid out on the chip, which mitigates against Privilege Escalation hardware backdoors. Exposure is limited to DoS attacks being planted into the silicon during FPGA fabrication, which yields a significantly improved level of assurance (i.e., the computer may stop working altogether, but can't betray its owner to an adversary while pretending to operate correctly). I suppose in theory the FPGA could contain a hidden CPU that has full read/write access to the FPGA program. Further, if the system becomes popular and more FPGAs need to be produced for the same system or the next generation, then the foundry has additional information and they can make a good guess of where the privilege bit will be. Even simpler, they could program an FPGA with the code and figure it out manually.
- duskwuff 2y ago> I suppose in theory the FPGA could contain a hidden CPU that has full read/write access to the FPGA program. Even if it did, it would be exceptionally difficult for that CPU to identify which registers/gates on the FPGA were being used to implement which components of the soft CPU. The layout isn't fixed; there's no consistent mapping of hardware LUTs/FFs to synthesized functionality.
- amelius 2y agoEven if the mapping changes, the network (graph of logic gates) will locally be similar. So a subgraph matching algorithm might be all that is needed.
- ruslan 2y agoI'm kind of going the same direction, but different route. My design is based on VexRiscv and all hardware is written in SpinalHDL. It does not run Linux yet because of limited SRAM (512KB) on my Karnix board, but it has Ethernet and HDMI. I have coded a CGA-like video adapter with HDMI interface that supports graphics (320x240x4) and text (80x30x16) modes with hardware assisted smooth scrolling. :) If someone is interested, here's a rather brief README: https://github.com/Fabmicro-LLC/VexRiscvWithKarnix/blob/karnix_extended/scripts/KarnixExtended/README.md https://github.com/Fabmicro-LLC/VexRiscvWithKarnix/blob/karn... KiCAD project for the board: https://github.com/Fabmicro-LLC/Karnix_ASB-254 https://github.com/Fabmicro-LLC/Karnix_ASB-254
- musicale 2y agoRebuilding the system on itself and validating that the bitfile is the same is nice. I'm amazed that it could be rebuilt in 512MB (and in "only" 4.5 hours on a ~65MHz CPU.) My experience with yosys (and vivado etc.) is that they seem to want many gigabytes. > A 65MHz Linux-capable CPU inevitably invokes memories of mid- 1990s Intel 486 and first-generation Pentium processors. 50-65MHz* and 512MB seems comparable to an early 1990s Unix workstation. Arguably better on the RAM side. *4.5 Mflops on double precision linpack for lowRISC/50MHz
- ranger_danger 2y agoThere's nothing free about FPGAs...
- mntmn 2y agoI did something similar in 2022, also with LiteX, but not self-hosting because it used a Kintex-7 FPGA which at least at the time required Vivado for the actual place-and-route. It did result in a open gateware laptop running Linux and Xorg, though (thanks to Linux-on-LiteX-VexRiscV): https://mntre.com/media/reform_md/2022-09-29-rkx7-showcase.html https://mntre.com/media/reform_md/2022-09-29-rkx7-showcase.h...
- indigodaddy 2y agoAll the good stuff is here looks like (linked in the op article): https://github.com/litex-hub/linux-on-litex-rocket https://github.com/litex-hub/linux-on-litex-rocket Cool, so didn’t know that you could use screen to connect to a tty/serial. Neat.
- dwheeler 2y agoThis is cool. I was happy see the prominent reference to my work on diverse double-compiling (DDC), which counters the trusting trust attack. If you're interested in DDC, check out https://dwheeler.com/trusting-trust https://dwheeler.com/trusting-trust
- rurban 2y ago(2020)
- rramadass 2y agoAlso see RISC-V based Shakti : Open Source Processor Development Ecosystem from IIT-Madras, India - https://shakti.org.in/ https://shakti.org.in/ Good overview at wikipedia - https://en.wikipedia.org/wiki/SHAKTI_(microprocessor) https://en.wikipedia.org/wiki/SHAKTI_(microprocessor)
- Rip_boy09929 2y ago[flagged]