2 ms·
Yes! It's one of those cases where when you've seen it before and know the catch with the instruction (probably vmovdqa) then you'll immediately recognise it.
by rwmj 2y ago
Yes! It's one of those cases where when you've seen it before and know the catch with the instruction (probably vmovdqa) then you'll immediately recognise it. If you don't know it, it's very very mysterious. Why on earth Intel decided to make a handful of instructions require alignment is also a mystery to me.
- jbosh 2y agoSweet mama speed. Although from what I understand it is more legacy speed cause you're losing all your time to fetching the memory anyway. But when processors were slower it was a meaningful amount.
- immibis 2y agoThe instruction wants to access one cache line, not two.
- fweimer 2y agoIt makes more sense now that Intel and AMD retconned naturally-aligned 128-bit atomic loads into the ISA: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688 (AMD's confirmation is in comment 10.)