3 ms·
am i missing something? since when does vitis connect to vivado and do the p&r too? anyway if you're tempted by this, i strongly advise you to ponder this: >
by almostgotcaught 2y ago
am i missing something? since when does vitis connect to vivado and do the p&r too?
anyway if you're tempted by this, i strongly advise you to ponder this:
> Run the Hardware build, should take around ~12 hours.
- dailykoder 2y agoWelcome to the world of FPGA synthesis :-) > am i missing something? since when does vitis connect to vivado and do the p&r too? I haven't done much HLS, but isn't that the normal case? Translating the HLS into HDL and then do the pnr with vivado?
- almostgotcaught 2y agoi've done plenty of FPGA and HLS as well > Translating the HLS into HDL and then do the pnr with vivado? As far as I know, vitis does not give you tcl scripts (or whatever) for vivado - you have to do that yourself.
- ChrisKjellqvist 2y agoI've been using HLS recently and from my understanding, all you need is `v++`. [link to example HLS makefile](https://github.com/Xilinx/Vitis_Accel_Examples/blob/f61637e9263ecc1be3df34182ea6c53a0ca10447/hello_world/Makefile#L135 https://github.com/Xilinx/Vitis_Accel_Examples/blob/f61637e9...)