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The Xtensa processor comes from Cadence and for some reason they like to keep everything under NDA, even information which would help people use their processor
by adolph 2y ago
The Xtensa processor comes from Cadence and for some reason they like to keep everything under NDA, even information which would help people use their processors. I find it hard to understand why the instruction set should be kept secret; a CPU vendor should make it as easy as possible for engineers to use their CPUs.
The P4 can't come soon enough to get off Xtensa.
- jsheard 2y agoThe P4 doesn't have a built-in radio though, so if you want those beefy RISC-V cores you will need to integrate a second ESP32 just to handle WiFi/BT :( It will have USB-OTG and an LCD driver at least, which so far have been missing from all of their RISC-V parts.
- ComputerGuru 2y agoCost optimization aside, that has always been the best way to use an ESP chip. Just go with one of their barebone models wired up as a peripheral to an ARM or RISC mcu.
- clbrmbr 2y agoYet it’s possible to build some incredible applications on top of just ESP32, especially with extra RAM.
- devmunchies 2y agoWe use esp32-s3 at my company (smart speaker) but we don't don anything fancy. Can you explain this? Why use esp as a peripheral if you already have an ARM chip? We were considering moving off of esp to something that would make it easier do cpu-bound AI inference on-device or to enable more advanced audio DSP algos.
- throwup238 2y agoBased on cost and development time, it’s usually just easier to add an ESP and communicate to it using a generic SPI library or something than to add a radio to your PCB and get vendor libraries working on an arbitrary platform.
- timschmidt 2y agoSeems likely they'll continue releasing more models, further integrating the features of the P4 and C6 for example. Maybe we'll even get some risc-v SIMD instructions and support for off-chip SRAM.
- antoniuschan99 2y agoI think that’s totally fine. Might actually be the future direction. But yea would’ve been nice to have wifi/bt integrated. Eg if you want 5ghz then use c5, or if you want some wifi-6 so c6, etc. Also here’s a talk by them on how to use esp as a wifi coprocessor https://youtu.be/g14aEjnjRLw?si=TgkEyJJ2_L_Shuom https://youtu.be/g14aEjnjRLw?si=TgkEyJJ2_L_Shuom There’s also adafruit airlift https://www.adafruit.com/product/4201 https://www.adafruit.com/product/4201
- Aurornis 2y ago> I think that’s totally fine. Might actually be the future direction. Using a second board just for WiFi is definitely not totally fine for most applications. Having everything integrated into a single package important for everything from reducing BOM count to lower power consumption to development simplicity.
- yau8edq12i 2y agoWithout the builtin radio it's really hard to justify the use of an ESP32 over, say, an STM32. The integrated small package with "everything" to make a fun project is the whole appeal.
- AlotOfReading 2y agoEspressif has a huge advantage in lead times over ST recently. I migrated a few projects over because ST couldn't or wouldn't give us supply in under a month when you could buy ESP chips and have them on your doorstep practically overnight.
- vbezhenar 2y agoDid you look at chinese STM clones? We used gd32, I liked it.
- 6SixTy 2y agoWide product range. ARM and RISC-V all called GD32 with an extra letter for the exact line.
- makapuf 2y agoDepends if you want to condone IP theft (compatible independent developments is of course different but I'm not sure this is the case). R&D, Support, good documentation in English and accuracy of specs come at a price.
- pantalaimon 2y agoIs implementing the same peripheral register API really IP theft?
- makapuf 2y agoNo, this was my remark about being compatible.
- sitkack 2y agoThe ESP8684H2 is 1.20 qty 1, more than enough to handle BT an Wifi, then you can use any MCU you want as your application processor.
- ajross 2y agoFWIW this bit in the article is a little confused. The SIMD instructions being detailed appear to be Espressif-custom things implemented using Cadence's "TIE" facility. Cadence does indeed have their own SIMD architecture ("HiFi", really it's a family of similar but binary-incompatible ISAs). And indeed docs for that don't appear in public (though if you look carefully, details for how to emit the instructions are part of the GNU toolchain integration). But that isn't this. If you want docs for this, talk to Espressif, not Cadence.
- mianos 2y agoIt is possible there is some licensing issue around the SIMD, after all it is an optional component. It was available for the LX6 as well, but not included. It's been a good run but it's great the are going to the RISCV, at the very least for the vibe. I have used both architectures, more recently using their esp-idf and it is surprisingly uneventful to switch between them. The only issue I had is the different high/low speed timer devices between chips. In fact it is a surprise the on chip peripheral hardware is incredibly compatible with their idf. Sure, they have a layer for some calls but a lot is just issuing commands to io devices directly, and the same between riskv and tensilkica cores.
- ajb 2y agoXtensa is an unusual beast because its USP (at least, back when it was owned by tensilica) was that you could easily add extensions. Not just off the shelf ones - ones you defined yourself. They had some automation that would generate a toolchain for you to use with your shiny new instructions. Most CPU architectures exist to allow programs written on once implementation to work on another, with Xtensa it's kind of the opposite - it exists to allow each chip to have its own special sauce. Honestly I was a bit surprised that espressif used it without defining their own extension of some kind, if you're not doing that then you might as well use something better known. Edit: ajross* points out that this SIMD extension is such a one, not an off the shelf one. So I guess that explains it. * https://news.ycombinator.com/item?id=40267977 https://news.ycombinator.com/item?id=40267977