4 ms·
The part about needing to be fluent in programming language research in order to understand the SAIL specification is a great point. I think it speaks to the or
by chrsw 3y ago
The part about needing to be fluent in programming language research in order to understand the SAIL specification is a great point. I think it speaks to the origins of RISC-V being by and for computer science or computer engineering academics and not for practicing digital designers for commercial systems.
- hajile 3y agoI believe the first cores in chisel which is a Haskell/ML type HDL, so SAIL fits right in. Just because people are used to other ways of doing things doesn’t make those ways better. “I don’t want to learn something new“ certainly isn’t a compelling argument.
- chrsw 3y agoLearning new things is good. This should be encouraged. But going from SystemVerilog to Chisel is not a small step. It's not really a question of what's better or worse. It's a paradigm shift in the way you think about how a design is captured and expressed. It's not like learning how to use a new dishwasher or driving a new car. It's learning a new stack of tools and flows. All under the pressure of delivering a new product on spec, on time and on budget. For many teams running in a tight cycle of design->tape out, it is not realistic to ask them to "learn something new". When you change the context, the perception changes. If you're a grad student who has chosen to dive head first into Chisel after already mastering functional programming and want to get more into hardware design, that's a different story.
- Peter_Sewell 3y agoNeither of these are actually the case: one doesn't need to be fluent in PL research to understand Sail specs (see @timhh comment above, forex), and Sail was developed independently of the origins of RISC-V.