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Zilog Z80 CPU – Modern, free and open source silicon clone
- Renaud 3y agoWhat Tiny Tapeout is doing is amazing. Who would have thought that makers and students could have their own chip design made real for so little money? The tools look amazing as well. You'll won't design the next Intel CPU on that 130nm process but to think that the Z80 will fit on 0.064 mm2 is just amazing. It's great that there will still be an alternative to the official chip now that it won't be manufactured any more. Now I want that gorgeous mauve ceramic package with a gold-plated cover over the chip... https://twitter.com/l_vanek/status/1783557817133039738/photo/1 https://twitter.com/l_vanek/status/1783557817133039738/photo... https://tinytapeout.com/ https://tinytapeout.com/
- chx 3y agoTo save a click > 160 x 100 um tile + ASIC + demonstration board: The standard price is $300 plus shipping. > However, Efabless is sponsoring a special early bird offer of $150 (plus shipping), limited to one order per person. > Each extra tile is $50, and extra analog pins start from $40 per pin. Unless I am badly mistaken 160 x 100 um is .16 x .1 mm which means the tile is 0.016 mm2 meaning a 0.064 mm2 die takes four slots?
- mk_stjames 3y agoYes it is taking up a 2x2 tile on the tinytapeout. https://app.tinytapeout.com/projects/668 https://app.tinytapeout.com/projects/668
- rowanG077 3y agoI could not find the pin capabilities. Is it possible to build an sdram controller or even drive ddr?
- ashleyn 3y ago130nm process puts them at roughly Pentium III era. Not bad!
- rvense 3y agoThat's wild. A Pentium III would still be useful in a pinch. How big was a P3 die, though?
- Someone 3y agohttps://en.wikipedia.org/wiki/Pentium_III#Katmai https://en.wikipedia.org/wiki/Pentium_III#Katmai: “The Katmai contains 9.5 million transistors, not including the 512 Kbytes L2 cache (which adds 25 million transistors), and has dimensions of 12.3 mm by 10.4 mm (128 mm²). It is fabricated in Intel's P856.5 process, a 250 nm complementary metal–oxide–semiconductor (CMOS) process with five levels of aluminum interconnect” That’s 2,000 times the area of this 0.064 mm² Z80. https://en.wikipedia.org/wiki/Pentium_III#Tualatin https://en.wikipedia.org/wiki/Pentium_III#Tualatin: “The third revision, Tualatin (80530), was a trial for Intel's new 130 nm process” I can’t easily find the die size if that.
- unnah 3y agoOn that kind of process, you could make a 1024-core Z80 machine, leaving half the area for memory, interconnect and I/O. With suitably smart programming and an embarrassingly parallel problem, it might even be able to beat a Pentium III in performance... although it looks like the single-core Pentium III can run 128-bit SSE instructions at 2 cycles per instruction.
- Someone 3y agoSuitably smart programming and a problem that suits the hardware. I doubt there are many of the latter. A Z80 has a 4-bit ALU (https://en.wikipedia.org/wiki/Zilog_Z80#Microarchitecture https://en.wikipedia.org/wiki/Zilog_Z80#Microarchitecture), making even integer addition take quite a few cycles (15 for 16-bit addition, reading http://www.z80.info/z80time.txt http://www.z80.info/z80time.txt) And then there’s the clock speed difference. The first Pentium III ran at 450MHz, the fastest Z80 at 50MHz (https://en.wikipedia.org/wiki/Zilog_eZ80 https://en.wikipedia.org/wiki/Zilog_eZ80) I think those two combined already will cost you a factor of around 100 in speed versus that pipelined Z80, much more versus a Z80 proper. Things get worse if you want to add or subtract 32- or 64-bit integers (another factor of 2 or 4, ballpark) If you want to do integer multiplication and division of any size and all floating point operations you will have to do those in software, and likely lose whatever speed advantage you might still have. O, and each core will be limited to 64kB of memory. Those interconnects better be fast and use DMA, so you can keep computing while you shuffle data around.
- belter 3y agoZ80 was the CPU of the ZX Spectrum. Oh the memories... https://en.wikipedia.org/wiki/ZX_Spectrum https://en.wikipedia.org/wiki/ZX_Spectrum
- mattl 3y agoSo many good machines: the Amstrad CPC range, a whole slew of Sega consoles, the early MSX stuff and of course the Tatung Einstein. 3 inch disk machines of the world unite!
- rwmj 3y agoNot to mention the world of CP/M business machines which was surprisingly large in the UK well into the late 80s, again thanks to Amstrad: https://en.wikipedia.org/wiki/Amstrad_PCW https://en.wikipedia.org/wiki/Amstrad_PCW
- flohofwoe 3y agoAll 8-bit computers manufactured in East Germany too (via the reverse enginered Z80 clone U880). For instance the KC85/2..4: https://floooh.github.io/virtualkc/p010_kc85.html https://floooh.github.io/virtualkc/p010_kc85.html An "Adrian's Digital Basement" episode about the KC85/3: https://www.youtube.com/watch?v=At9UNYFHuaE https://www.youtube.com/watch?v=At9UNYFHuaE
- mchannon 3y agoYou forgot about Donkey Kong (and Junior, and 3, and Mario Bros.) Punch-Out!! But most noteworthy is Galaga: Ran on 3, count 'em, 3, Z80's.
- flohofwoe 3y ago...also Pacman btw (the original arcade machine), and other 80's arcade machines like Pengo or Bomb Jack (notably Bomb Jack was two Z80 computers duct-taped together, the sound was handled by a separate Z80 board which controlled three AY-3-8910 sound chips).
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- Retr0id 3y agoDoes anyone know what clock speeds we might be able to expect from this?
- drmpeg 3y agoThis page says 50 MHz. https://github.com/rejunity/z80-open-silicon/blob/main/docs/info.md https://github.com/rejunity/z80-open-silicon/blob/main/docs/...
- tyingq 3y agoInteresting. Saw this on the Wishbone Z80 project notes: "Guy Hutchison (see TV80 project) has synthesized an early version of the core in a 130nm TSMC process. He determined the design to contain about 20k gates and run at about 240 Mhz. While the speed is somewhat less than "target", optimizations of the logic should increase this somewhat." Guy Hutchison's TV80 is also mentioned on this project's page.
- swetland 3y agoThat's the expected clock rate for the TT07 run... but Tiny Tapeout designs only have 8 in, 8 out, and 8 bidirectional IOs (plus a reset and clock input) available, so they're using a multiplexing strategy where the Z80 clock runs at 1/4 of the base clock rate and alternates between control signals, A0-A7, control signals, and A8-A15 on the OUT pins: https://github.com/rejunity/z80-open-silicon/blob/68438f00192e7b2388163e198b330567e6133cb7/src/tt_um_rejunity_z80.v#L24 https://github.com/rejunity/z80-open-silicon/blob/68438f0019... So you'd get an effective 12.5MHz Z80 clock and need a bit of external logic to demultiplex the full IO interface. Still not too shabby! The goal (per the project README) appears to be to prototype with TT07 and then look into taping out standalone with ChipIgnite in QFN44 and DIP40 packages (which would be able to have the full traditional Z80 bus interface and run at the full clock rate).
- Dwedit 3y agoIf you were designing a new compatible processor for older systems, the limiting factor would be the memory bus. A cache would be necessary to get high speeds. The cache would need to know about all bank-switching performed by the system, and understand how the memory banks are mapped into the memory space. Could have: * Plain read-only memory (you cache this) * Plain RAM not shared with other devices (you cache this) * Memory-mapped IO (you don't cache this) * RAM shared with other devices where the other device does not write there, such as video memory (write-through cache, full read cache) * RAM shared with other devices where the other device can write there (don't cache this)
- robxorb 3y agoFor those wondering, the 6502 and various derivatives are still being manufactured, by one of its original creators [0] - so I'd guess an equivalent development in the world of the Z80's nemesis is unlikely anytime soon. [0] https://www.westerndesigncenter.com/wdc/chips.php https://www.westerndesigncenter.com/wdc/chips.php
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- ksherlock 3y ago65*C*02, which might fail if your 6502 code depends on illegal opcodes or incidental memory access or BCD math cycle timing or BCD math flags or perhaps decimal mode being set in an interrupt routine.
- grumpyprole 3y agoThe 65C02 came out in 1983, so I think we've had plenty of time to document and workaround these issues!
- giantrobot 3y agoHey, don't touch my space heater![0] [0] https://xkcd.com/1172/ https://xkcd.com/1172/
- zczc 3y agoAnd eZ80 (binary compatible, but not pin-compatible with Z80) is still being manufactured by Zilog.
- monocasa 3y agoInterestingly the classic z80 was end of lifed just two weeks ago. https://hackaday.com/2024/04/19/end-of-life-for-z80-cpu-and-peripherals-announced/ https://hackaday.com/2024/04/19/end-of-life-for-z80-cpu-and-...
- Koshkin 3y agoI couldn’t help but notice that the circuit layout looks like a uniform gate array rather something resembling a custom layout you usually see in die photos.
- flohofwoe 3y agoBecause it's a Verilog implementation which is much closer to a software CPU emulator than the real thing (e.g. it has nothing to do with the original Z80 "transistor layout"). For instance here's the LD A,(DE) "instruction payload": https://github.com/rejunity/z80-open-silicon/blob/974c7711b21a4d71c083b8dd19e1e2b082b597ce/src/tv80/tv80_mcode.v#L352-L360 https://github.com/rejunity/z80-open-silicon/blob/974c7711b2... And here's the same machine cycle in my software emulator: https://github.com/floooh/chips/blob/bd1ecff58337574bb46eba5e7e16937899360e56/chips/z80.h#L2082-L2088 https://github.com/floooh/chips/blob/bd1ecff58337574bb46eba5... Both set the address bus to the content of the DE register (and at the same time the MREQ|RD pins need to be set somewhere to indicate a memory read to the outside world, in my emulator this happens in the _mread macro), and in the next clock cycle load the data bus into the A register. What's interesting though is that the Verilog implementation doesn't seem to update the internal WZ register with DE+1, which makes me wonder if undocumented behaviour is correctly implemented, but maybe updating WZ is handled elsewhere (there are references to the WZ register in other places). In the end, if it looks and feels like a Z80 from the outside (e.g. the right pins are active at the right time) the internal implementation doesn't matter.
- rowanG077 3y agoJust because this is done in verilog doesn't make it emulation. It's probably just machine placed and routed. Almost everything is these days in digital design.
- flohofwoe 3y agoBut look here, it's even doing a switch-case over the opcode, which is very typical for a software CPU emulator: https://github.com/rejunity/z80-open-silicon/blob/974c7711b21a4d71c083b8dd19e1e2b082b597ce/src/tv80/tv80_mcode.v#L273 https://github.com/rejunity/z80-open-silicon/blob/974c7711b2... Instruction decoding on a real Z80 CPU doesn't work at all like that :) A non-emulator-approach would probably use the reverse engineered Z80 netlist from visual6502.org to base the design on, no idea if this is even doable with modern chip design tooling(?) If anything, the netlist is useful to verify the Verilog implementation (as is mentioned here in the readme: https://github.com/rejunity/z80-open-silicon?tab=readme-ov-file#further-plan--todo https://github.com/rejunity/z80-open-silicon?tab=readme-ov-f...)
- tcbawo 3y agoI had heard about Z80’s 4-bit ALU (2x for 8-bit math). Is this considered a major bottleneck? Were there later extensions that added higher bit integer math? I’m curious whether an open source version of the chip will enable new features and variants.
- flohofwoe 3y ago> Is this considered a major bottleneck? No, because an ALU instructions with a register as source is already running as fast as possible (at 4 clock cycles, which is the duration of an opcode fetch 'machine cycle'). Or from a different perspective: an 8-bit ALU wouldn't have made math instructions faster, but would have cost twice as many transistors. The 4-bit ALU is just an internal implementation detail that isn't visible to the outside (except maybe through the existence of the half-carry flag which indicated a carry from the lower into the higher nibble). And if you want a CPU replacement that plugs directly into old home computers, the CPU needs to have the original instruction timing, otherwise software that depends on 'cycle counting' won't work (probably less of an issue on the ZX Spectrum though because the Speccy didn't have a programmable video hardware like for instance the Amstrad CPC). The eZ80 is a modernised and more efficient design, with (among other things) a wider ALU: https://en.wikipedia.org/wiki/Zilog_eZ80 https://en.wikipedia.org/wiki/Zilog_eZ80. Not an option for keeping old home computers alive though, for this you'd want an exact Z80 clone with the original timings and undocumented behaviour.
- becurious 3y agoCycle counting was key on the Spectrum - for obvious things like the tape load routines but also for advanced techniques like the ‘Rainbow processor’ - updating the attribute bytes (those responsible for the infamous color clash) as each scan line progressed you could get different colors on each scan line.
- flohofwoe 3y ago> ...updating the attribute bytes (those responsible for the infamous color clash) as each scan line progressed... Ah clever! Didn't think of that. Probably the closest thing to "racing the beam" since the Atari 2600 :)
- rsynnott 3y agoWow. Just looked it up; the Z80 is now _50 years old_.
- phendrenad2 3y agoI wonder if this will ever be priced competitively with the massive number of used or NOS Z80 chips out in the wild.
- ein0p 3y agoeBay says a Chinese Z80 clone is less than $4 with free shipping. This isn’t even going to be competitive with lower end FPGAs. It’s more of a fun “why not” type of project.
- londons_explore 3y agoHow do those clones work? Are they asics, or microcontrollers/fpga's which do emulation?
- tredre3 3y agoThey're ASICs. Likely a direct copy of Zilog's design but I'm sure re-implementations also exist. I've never received a counterfeit Z80 that outright didn't work, but one thing to be keep in mind is that despite often being branded as CMOS 20Mhz (aka Z84C0020), half the time the chips I've received were lower grade or even worse, NMOS.
- kumarski 3y agoLooks dope. (I was on early efabless.com team) open source EDA.
- userbinator 3y agoI wonder how compatible it is with the original Z80, which had many undocumented instructions as well as the infamous "trap gates" (look at the "Oral History Panel on the Founding of the Company and the Development of the Z80 Microprocessor" documented linked on that page) that might've had an effect on certain obscure instruction sequences and designed to identify the difference between it and clones.
- mindcrime 3y agoSo, um... you're saying I should not have dumped my life's savings into ordering Z80 chips as part of the "last time buy"? :-(
- MisterTea 3y agoI think the real joy of these old 8-bit CPU's is the simplicity and how a single person can wire up a computer by hand. In uni we built an 8088 board in microprocessor class and it was the best class I ever took; it demystified drivers and hardware for me. I attempted a redesign using KiCAD which added an IO expansion port and better layout with an LCD port for a 2x16 character LCD. I had a prototype made by Futurlec but made a massive mistake in footprint assignment that required an interposer. Furthest I got was soldering in the 8284 and the IC sockets then got distracted by life and its sitting in a box still. Microcontrollers are great, everything in one package but there's something enormously satisfying about being able to design and build a computer by hand. FPGAs sort of bring this back but the tooling is byzantine dog shit.
- avnd 3y agoThe open source tooling isn’t perfect but it’s growing fast! I work in this space and recommend checking out the OpenROAD[1] project, which has full synthesis and pnr for select FPGAs. [1] https://theopenroadproject.org/ https://theopenroadproject.org/