4 ms·
OP isn't wrong. Once the switch was made from 2D to 3D gates, transistor numbering became "this is the performance you would expect if you COULD shrink a gate
by s3p 2y ago
OP isn't wrong. Once the switch was made from 2D to 3D gates, transistor numbering became "this is the performance you would expect if you COULD shrink a gate to x nm", and while it's inaccurate it lets people understand how differentiated a new generation is from the previous ones. It also lets them stay consistent with understanding the progression of chips over time as in most of the history of silicon the generations were defined by the gates' nm sizing.
- hinkley 2y agoWe should have switched to gates per mm² long ago. IMO that covers the 3D problem fine. Doesn’t cover variance in feature size by task though. If the gates for a multiplier or cache need more space per gate than a logical OR then the marketing guys still get a little victory over truth. We could just divide total gates by surface area for the chip, but that would confuse the process efficiency with the implementation details and then we sacrifice instructions per second for a marketing number.
- fennecbutt 2y agoI'd say mm3 really, means it works going into the future when we can hopefully make something like a 10mm3 chunk of silicon. Gimme that computronium!
- hinkley 2y agoWe know that height is a thermal dissipation issue. If someone can figure out how to make taller chips then good for them. Any time a chip goes vertical you also reduce speed of light delay between units, so it still has effects we desire and want to push. mm² is perfectly adequate for what we are after.