4 ms·

Nope that's what it meant a long time ago. Nowadays, the nm number represents the smallest possible element on the chip, typically the gate length, which is sma

Nope that's what it meant a long time ago. Nowadays, the nm number represents the smallest possible element on the chip, typically the gate length, which is smaller than the size of a transistor. This means that when different manufacturers use a different transistor design, their 'nm' process could be the same but their transistor density different.

yau8edq12i 2y ago
No, it's not even related to gate length or any kind of physical feature anymore. It's a purely marketing term. A "3 nm" node has a gate length around 16-18 nm.
- s3p 2y ago
  OP isn't wrong. Once the switch was made from 2D to 3D gates, transistor numbering became "this is the performance you would expect if you COULD shrink a gate to x nm", and while it's inaccurate it lets people understand how differentiated a new generation is from the previous ones. It also lets them stay consistent with understanding the progression of chips over time as in most of the history of silicon the generations were defined by the gates' nm sizing.
  - hinkley 2y ago
    We should have switched to gates per mm² long ago. IMO that covers the 3D problem fine. Doesn’t cover variance in feature size by task though. If the gates for a multiplier or cache need more space per gate than a logical OR then the marketing guys still get a little victory over truth. We could just divide total gates by surface area for the chip, but that would confuse the process efficiency with the implementation details and then we sacrifice instructions per second for a marketing number.
    - fennecbutt 2y ago
      I'd say mm3 really, means it works going into the future when we can hopefully make something like a 10mm3 chunk of silicon. Gimme that computronium!
      - hinkley 2y ago
        We know that height is a thermal dissipation issue. If someone can figure out how to make taller chips then good for them. Any time a chip goes vertical you also reduce speed of light delay between units, so it still has effects we desire and want to push. mm² is perfectly adequate for what we are after.
- maqp 2y ago
  I don't see it as an issue if the marketing term maintains the original context: "how large a planar FET should be for the transistor density used in this process" Is this the case, I'm not entirely sure. If it is, there be a better unit for this measurement, absolutely. PLANETS: PLANar Equivalent Transistor Size Or hire a marketing team to figure a good one.
0x457 2y ago
Not even that. Those numbers just mean, "this 3D 2nm-ish process performs similar to a 2D 2nm process". It's the same situation as when AMD started putting numbers in their Athlon XP SKUs to tell "this CPU performs just as good as intel of that frequency". I, for one, think it makes sense. Because as I consumer I don't care about actual transited length or density, all I care about is: performance, efficiency, price. I can assume that going from TSMC N5 to TSMC N3 would result in an increase in efficiency and performance. People that do care about those things (i.e. electrical engineers) most likely don't use marketing materials...
audunw 2y ago
You have it the wrong way around. The nm number used to mean minimum gate length. But when moving to FinFET and other transistor innovations that provided increased density, they decreases the “nm” number AS IF the increased transistor density came from shrinking gate length with a traditional planar transistor. The nm has always been a very rough approximate proxy for transistor density. Nothing has really changed about how what the number implies. I find it so weird how so many people on hacker is so hung up on the “nm” numbering. None of these people are designing standard cell libraries and those that actually design standard cell libraries never cared about what’s in the marketing material anyway. Lowe number means higher transistor density in some ways, on some parts of the chip. That’s all

yau8edq12i 2y ago

No, it's not even related to gate length or any kind of physical feature anymore. It's a purely marketing term. A "3 nm" node has a gate length around 16-18 nm.

s3p 2y ago
OP isn't wrong. Once the switch was made from 2D to 3D gates, transistor numbering became "this is the performance you would expect if you COULD shrink a gate to x nm", and while it's inaccurate it lets people understand how differentiated a new generation is from the previous ones. It also lets them stay consistent with understanding the progression of chips over time as in most of the history of silicon the generations were defined by the gates' nm sizing.
- hinkley 2y ago
  We should have switched to gates per mm² long ago. IMO that covers the 3D problem fine. Doesn’t cover variance in feature size by task though. If the gates for a multiplier or cache need more space per gate than a logical OR then the marketing guys still get a little victory over truth. We could just divide total gates by surface area for the chip, but that would confuse the process efficiency with the implementation details and then we sacrifice instructions per second for a marketing number.
  - fennecbutt 2y ago
    I'd say mm3 really, means it works going into the future when we can hopefully make something like a 10mm3 chunk of silicon. Gimme that computronium!
    - hinkley 2y ago
      We know that height is a thermal dissipation issue. If someone can figure out how to make taller chips then good for them. Any time a chip goes vertical you also reduce speed of light delay between units, so it still has effects we desire and want to push. mm² is perfectly adequate for what we are after.
maqp 2y ago
I don't see it as an issue if the marketing term maintains the original context: "how large a planar FET should be for the transistor density used in this process" Is this the case, I'm not entirely sure. If it is, there be a better unit for this measurement, absolutely. PLANETS: PLANar Equivalent Transistor Size Or hire a marketing team to figure a good one.

0x457 2y ago

Not even that. Those numbers just mean, "this 3D 2nm-ish process performs similar to a 2D 2nm process". It's the same situation as when AMD started putting numbers in their Athlon XP SKUs to tell "this CPU performs just as good as intel of that frequency". I, for one, think it makes sense. Because as I consumer I don't care about actual transited length or density, all I care about is: performance, efficiency, price. I can assume that going from TSMC N5 to TSMC N3 would result in an increase in efficiency and performance. People that do care about those things (i.e. electrical engineers) most likely don't use marketing materials...

audunw 2y ago

You have it the wrong way around. The nm number used to mean minimum gate length. But when moving to FinFET and other transistor innovations that provided increased density, they decreases the “nm” number AS IF the increased transistor density came from shrinking gate length with a traditional planar transistor. The nm has always been a very rough approximate proxy for transistor density. Nothing has really changed about how what the number implies. I find it so weird how so many people on hacker is so hung up on the “nm” numbering. None of these people are designing standard cell libraries and those that actually design standard cell libraries never cared about what’s in the marketing material anyway. Lowe number means higher transistor density in some ways, on some parts of the chip. That’s all