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JEDEC Extends DDR5 Memory Spec to 8800 MT/S, Adds Anti-Rowhammer Features
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- theandrewbailey 3y ago> Unfortunately, the laws of physics driving DRAM cells have not improved much over the last couple of years (or decades, for that matter), so memory chips still must operate with similar absolute latencies, driving up the relative CAS latency. In this case 14ns remains the gold standard, with CAS latencies at the new speeds being set to hold absolute latencies around that mark. Some gaming memory kits can do 10ns or less latency. Though I guess if memory latency is your bottleneck, you should look at HBM.
- spintin 3y agoHBM is slower than DDR per pin, the speed gain is from a hugely parallel bus. Parallel means latency if you have non "embarrassingly parallelizable" tasks?
- Tuna-Fish 3y agoThe smallest transfer done from memory is a single cache line, which on most desktop machines is 64 bytes, or 512 bits. You could imagine a memory bus that was 512 bits wide and transferred a cache line per clock, and this would improve latency when compared to a serial bus with higher clock speed. HBM doesn't do that, though, instead every HBM3 module has 16 individual 64-bit channels, with 8n prefetch (that is, when you send a single request to a single channel, it will respond with 512 bits over 8 cycles).
- dist-epoch 3y agoDDR5 has 2 independent 32-bit lanes. Multiple transfers are required for 64 bytes.
- Tuna-Fish 3y agoDDR5 has a 16n prefetch, so a single transfer from a 32-wide channel moves 64 bytes.
- moffkalast 3y agoI don't think they make HBM RAM kits. /s
- Night_Thastus 3y agoI'm a bit confused, DDR5 products are already out - as are CPUs and motherboards that support them. How can this change happen retroactively? Would motherboard manufacturers just need to update the BIOS to enable new XMP configurations? (For when this new, higher transfer rate RAM becomes available)
- braiamp 3y ago> while leaving the spec open to further expansions with faster memory as technology progressed They only set the current standard, but allowed to, if technology progresses, that other speeds/timings would also be jedec compatible, rather than being some kind of XMP. Motherboard manufacturers do not need to upgrade their previous models if the hardware doesn't meet the required SN ratios, or whatever. But they _could_ if they believe they had the hardware to support it.
- tadfisher 3y agoNot even that; this just sets standard speed/latency values for memory modules without XMP. You can already exceed these numbers with XMP. PRAC would need handling in the memory controller, so that would require a CPU update if I understand correctly.
- doikor 3y agoPRAC should happen automatically in the background when possible and when it really needs to stop the controller from accessing something while waiting for the bits to refresh it uses the already existing ALERTn signal. https://stefan.t8k2.com/rh/PRAC/index.html https://stefan.t8k2.com/rh/PRAC/index.html > Panopticon retrofits an existing signal in the DDR specification, called ALERTn, to effectively “trick” the memory controller to pause issuing new DDR commands. DRAM uses ALERTn to signal errors to the memory controller. Upon receiving this signal, the memory controller stops issuing new DRAM commands and instead re-issues the old memory access. By making use of ALERTn, Panopticon requires no modifications to any hardware other than DRAM itself. (As I understand PRAC uses the same design as Panopticon for this part)
- dist-epoch 3y ago
- londons_explore 3y agoI'd like to see the spec tackle latency with a "send then confirm" approach. Ie. The RAM can reply to a read request with data, then a couple of clock cycles later it can confirm (via a flag) that the data it originally sent was correct. This is helpful because it means the timing can be tightened to the typical access times, rather than the worst case access time (eg. the slowest preamp on the highest capacitance memory row/column). Things like CPU's already have provisions for handling not-yet-confirmed information, and can roll back state if delivered info turns out to be wrong. Yes, it adds complexity to the whole system, but it seems worth it for a -30% change to memory latency.
- pshirshov 3y agoAnd potentially opens a whole new family of side channels.
- touisteur 3y agoI wish we could mix 'I don't care about side channels, use them all' with 'I'm paranoid about side channels, plug them all' on the same machine. Disable speculative execution on one core, no frequency adjustment, no prefetching, sr-io/pcie-bypass some devices... E-cores but for the side-channel-paranoid (in a good way).
- smallmancontrov 3y agoBring back EIEIO, like on Old Macs, but perhaps with a slightly expanded definition of what constitutes I/O: Enforce In-order Execution of I/O (EIEIO) is an assembly language instruction used on the PowerPC central processing unit (CPU) which prevents one memory or input/output (I/O) operation from starting until the previous memory or I/O operation completed. This instruction is needed ] as I/O controllers on the system bus require that accesses follow a particular order, while the CPU reorders accesses to optimize memory bandwidth usage.
- colejohnson66 3y ago
- AzzyHN 3y agoI'm always a fan of bigger numbers, but I wish more time/money/whatever was put into letting DDR5 run at those XMP/EXPO speeds when using 4 DIMMs.
- imtringued 3y agoHow do you expect that to happen? By sharing memory channels you are no longer using a point to point connection and are now prone to reflections in the PCB traces where you have split the signal. There is no "money" that can be put into this, that won't also improve the performance of the single DIMM per channel setup disproportionately. I don't even understand what your point is. Quad channel support would be a much better idea since it doubles your memory bandwidth, while remaining a point to point connection, but you're going to complain that you can't add eight DIMMs then.
- zrm 3y agoWhat if you give each slot independent command pins but not a complete memory channel? What if you use a similar technology to registered or load-reduced memory, but put the register on the system board instead of the DIMM so it's in front of multiple DIMMs that then share the channel into the processor but not the traces on the system board? This may also allow higher capacity DIMMs in consumer systems.
- atlas_hugged 3y agoYou doing ok dude?
- Aurornis 3y ago4 DIMMs on a consumer board means 2 DIMMs per channel. This is inherently a compromise in signal integrity that must come with a speed tradeoff, unfortunately. We’re dealing with laws of physics. In the past some motherboards tried a T-topology for RAM slots to optimize for 2 DIMMs per channel, but this would cause problems with 1 DIMM per channel usage. Not worth it for the average consumer.
- smolder 3y agoThe way to do that would be with a chip & socket that has 4 independent memory channels (threadripper I think has eight now, but maybe used to have four?) and a many-layered motherboard that optimizes the routing and placement of each dimm slot, ideally with only 1 dimm slot per channel for maximum speed. The high end stuff with many memory channels generally isn't designed for pushing RAM clocks to gaming desktop speeds, though. You'd probably need to skip on ECC too or overclock and manually time some.
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- oneplane 3y agoThe article doesn't mention much about chip-to-controller distance or path length, presumably this suffers from the same issues we currently see where low power devices (and in some desktop configurations as well) can't really ever get those speeds unless the DRAM chips are near or on top of the CPU substrate. It's nearly impossible to do those numbers in modern mobile form factors, even CAMM is having a hard time getting there with modularised memory.
- Aurornis 3y agoGenerally the highest speeds aren’t intended for low power devices. They’re targeted at applications where performance is the most important goal and the power tradeoffs are not an issue. Enthusiast motherboards and RAM kits can already exceed these speeds. Having official JEDEC timings just makes these speed a more universal target for long-term high end designs.
- oneplane 3y agoWhile that's true, It's also true that mobile devices tend to be a rather static configuration during their lifetime, and if you're going to have a fleet of those, having the best performance during that lifetime is a nice bonus. So I believe that form factor specific considerations are still a good value to write about.
- snvzz 3y agoPlease make ECC mandatory.
- wmf 3y agoIt's never going to happen because Dell counts every penny.
- deleted 3y ago[deleted]
- snvzz 3y agoJEDEC could only standardize ECC modules. Microsoft, Intel or AMD can, anytime, require ECC for their certification/logo programs. Intel and AMD could even make their new chips only boot with ECC. And FCC could make ECC a requirement for certification. All these parties (and more) are enabling non-ECC memory, to the detriment of mankind.
- _factor 3y agoI prefer my computations have unreported errors at the whim of explosions billions of light years away. Makes me feel connected to the universe.
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- transpute 3y agohttps://stefan.t8k2.com/rh/PRAC/index.html https://stefan.t8k2.com/rh/PRAC/index.html Chapter 16: "DDR5 Per Row Activation Counting (PRAC)". PRAC introduces two key mechanisms for comprehensive Rowhammer defenses: an Activation Counter for every DRAM row and a mechanism that triggers when an Activation Counter reaches a specific threshold. This allows the DRAM to pause the memory controller from issuing new commands, giving it time to refresh potential victim rows. In the words of a DRAM industry veteran who will remain nameless, PRAC is the biggest change to DRAM in decades. Thus, I thought I should write up a brief article summarizing the change and its potential to solve Rowhammer once and for all.
- nneonneo 3y agoI'll bet good money that this gets turned into a timing attack soon - it's a prototypical address-dependent delay.
- oakwhiz 3y agoI kind of feel like JEDEC isn't taking the problem seriously.
- chuckadams 3y agoAren’t there already timing attacks based on cache latency?
- teaearlgraycold 3y agoOh my god! Rate limiting for RAM. The realities of security sure are harsh.
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