3 ms·
well, the interesting part here is that the tools (verilog and openlane) seem to work pretty well and are highly accessible. designing a cpu hasn't been a comp
by markhahn 2y ago
well, the interesting part here is that the tools (verilog and openlane) seem to work pretty well and are highly accessible. designing a cpu hasn't been a complicated exercise for decades, but implementing it has been.
- IshKebab 2y agoVerilog is kind of trash by modern standards. Unfortunately we are stuck with it (well SystemVerilog) until tool vendors support something else. It's kind of a similar situation to JavaScript actually. And in a similar way, you can compile to Verilog, but just like with JS it makes debugging much more painful. There was this interesting project but it seems inactive: https://llhd.io/ https://llhd.io/ There's also various alternative HDLs that seem to have various levels of solving the wrong problem (SpinalHDL, MyHDL, Chisel). This one looks quite interesting though: https://filamenthdl.com/ https://filamenthdl.com/