3 ms·
I think a quick 2-minute read on the changes around each generation gen1 -> gen4 example from 2016 will make it a bit clearer [0]. Things like packet encoding
by dvas 2y ago
I think a quick 2-minute read on the changes around each generation gen1 -> gen4 example from 2016 will make it a bit clearer [0].
Things like packet encoding etc. Then a quick look at the signalling change of NRZ vs PAM4 in later generations.
Gen1 -> Gen5 used NRZ, PAM4 is used in PCIe6.0.
[0] Understanding Bandwidth: Back to Basics, Richard Solomon, 2016:
https://www.synopsys.com/blogs/chip-design/pcie-gen1-speed-basics.html https://www.synopsys.com/blogs/chip-design/pcie-gen1-speed-b...
- Dylan16807 2y agoI don't think that makes the answer to the question clearer at all. The slight differences in encoding are interesting but they don't answer the big question: They made a significant signalling change once, with 6. How did they manage to take the baud rate from 5 to 8 to 16 to 32 GHz?
- dvas 2y agoTo go a bit deeper, while still keeping it at a very high level what changes were made between each generation: PCIe 1.0 & PCIe 2.0: Encoding: 8b/10b PCIe 2.0 -> PCIe 3.0 transition: Encoding changed from 8b/10b to 128b/130b, reducing bandwidth overhead from 20% to 1.54. Changes here in the actual PCB material to allow for higher frequencies. Like changing away from PCB material like FR-4 to something else [2]. PCIe 3.0, PCIe 4.0, PCIe 5.0: Encoding: 128b/130b There is plenty to dive deep on, things like: - PCB Material for high-frequency signals (FR4 vs others?) - Signal integrity - Link Equalization - Link Negotiation Then decide which layer of PCIe to look at: - Physical - Data / Transmission - Link Layer - Transaction A good place to read more is from the PCI-SIG FAQ section for each generation spec that explains how they managed to change the baud rate as you mentioned. PCI-SIG, community responsible for developing and maintaining the standardized approach to peripheral component I/O data transfers. PCIe 1.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_express https://pcisig.com/faq?field_category_value%5B%5D=pci_expres... PCIe 2.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_express_2.0 https://pcisig.com/faq?field_category_value%5B%5D=pci_expres... PCIe 3.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_express_3.0 https://pcisig.com/faq?field_category_value%5B%5D=pci_expres... PCIe 4.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_express_4.0 https://pcisig.com/faq?field_category_value%5B%5D=pci_expres... PCIe 5.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_express_5.0 https://pcisig.com/faq?field_category_value%5B%5D=pci_expres... PCIe 6.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_express_6.0 https://pcisig.com/faq?field_category_value%5B%5D=pci_expres... PCIe 7.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_express_7.0 https://pcisig.com/faq?field_category_value%5B%5D=pci_expres... [0] Optimizing PCIe High-Speed Signal Transmission — Dynamic Link Equalization https://www.graniteriverlabs.com/en-us/technical-blog/pcie-dynamic-link-equalization https://www.graniteriverlabs.com/en-us/technical-blog/pcie-d... [1] PCIe Link Training Overview, Texas Instruments [2] PCIe Layout and Signal Routing https://electronics.stackexchange.com/questions/327902/pcie-layout-and-signal-routing https://electronics.stackexchange.com/questions/327902/pcie-...